X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.c;h=90e1a00f08e6eac45c21940a2631244b1238675a;hb=b85dcae447581d06013cb7d68f582a8708c3cc50;hp=933b42e4ce004719a4c0bbec3129909efe2edf43;hpb=8d1dcb9bcde55ff29c1967d86c5f8985620df923;p=openocd.git

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 933b42e4ce..90e1a00f08 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -39,6 +39,7 @@
 #include "target_request.h"
 #include "target_type.h"
 #include "arm_opcodes.h"
+#include <helper/time_support.h>
 
 static int cortex_a8_poll(struct target *target);
 static int cortex_a8_debug_entry(struct target *target);
@@ -88,16 +89,28 @@ static int cortex_a8_init_debug_access(struct target *target)
 	/* The debugport might be uninitialised so try twice */
 	retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
 	if (retval != ERROR_OK)
-		mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
+	{
+		/* try again */
+		retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
+		if (retval == ERROR_OK)
+		{
+			LOG_USER("Locking debug access failed on first, but succeeded on second try.");
+		}
+	}
+	if (retval != ERROR_OK)
+		return retval;
 	/* Clear Sticky Power Down status Bit in PRSR to enable access to
 	   the registers in the Core Power Domain */
 	retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
+	if (retval != ERROR_OK)
+		return retval;
+
 	/* Enabling of instruction execution in debug mode is done in debug_entry code */
 
 	/* Resync breakpoint registers */
 
-	/* Since this is likley called from init or reset, update targtet state information*/
-	cortex_a8_poll(target);
+	/* Since this is likely called from init or reset, update target state information*/
+	retval = cortex_a8_poll(target);
 
 	return retval;
 }
@@ -359,11 +372,22 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
 	int retval;
 
 	/* set up invariant:  INSTR_COMP is set after ever DPM operation */
-	do {
+	long long then = timeval_ms();
+	for (;;)
+	{
 		retval = mem_ap_read_atomic_u32(swjdp,
 				a8->armv7a_common.debug_base + CPUDBG_DSCR,
 				&dscr);
-	} while ((dscr & DSCR_INSTR_COMP) == 0);
+		if (retval != ERROR_OK)
+			return retval;
+		if ((dscr & DSCR_INSTR_COMP) != 0)
+			break;
+		if (timeval_ms() > then + 1000)
+		{
+			LOG_ERROR("Timeout waiting for dpm prepare");
+			return ERROR_FAIL;
+		}
+	}
 
 	/* this "should never happen" ... */
 	if (dscr & DSCR_DTR_RX_FULL) {
@@ -646,21 +670,38 @@ static int cortex_a8_halt(struct target *target)
 	 */
 	retval = mem_ap_write_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DRCR, 0x1);
+	if (retval != ERROR_OK)
+		goto out;
 
 	/*
 	 * enter halting debug mode
 	 */
-	mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
+	retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
+	if (retval != ERROR_OK)
+		goto out;
+
 	retval = mem_ap_write_atomic_u32(swjdp,
 		armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
-
 	if (retval != ERROR_OK)
 		goto out;
 
-	do {
-		mem_ap_read_atomic_u32(swjdp,
+	long long then = timeval_ms();
+	for (;;)
+	{
+		retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DSCR, &dscr);
-	} while ((dscr & DSCR_CORE_HALTED) == 0);
+		if (retval != ERROR_OK)
+			goto out;
+		if ((dscr & DSCR_CORE_HALTED) != 0)
+		{
+			break;
+		}
+		if (timeval_ms() > then + 1000)
+		{
+			LOG_ERROR("Timeout waiting for halt");
+			return ERROR_FAIL;
+		}
+	}
 
 	target->debug_reason = DBG_REASON_DBGRQ;
 
@@ -675,6 +716,7 @@ static int cortex_a8_resume(struct target *target, int current,
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct arm *armv4_5 = &armv7a->armv4_5_common;
 	struct adiv5_dap *swjdp = &armv7a->dap;
+	int retval;
 
 //	struct breakpoint *breakpoint = NULL;
 	uint32_t resume_pc, dscr;
@@ -758,12 +800,25 @@ static int cortex_a8_resume(struct target *target, int current,
 	 * REVISIT: for single stepping, we probably want to
 	 * disable IRQs by default, with optional override...
 	 */
-	mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
+	retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
+	if (retval != ERROR_OK)
+		return retval;
 
-	do {
-		mem_ap_read_atomic_u32(swjdp,
+	long long then = timeval_ms();
+	for (;;)
+	{
+		retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DSCR, &dscr);
-	} while ((dscr & DSCR_CORE_RESTARTED) == 0);
+		if (retval != ERROR_OK)
+			return retval;
+		if ((dscr & DSCR_CORE_RESTARTED) != 0)
+			break;
+		if (timeval_ms() > then + 1000)
+		{
+			LOG_ERROR("Timeout waiting for resume");
+			return ERROR_FAIL;
+		}
+	}
 
 	target->debug_reason = DBG_REASON_NOTHALTED;
 	target->state = TARGET_RUNNING;
@@ -804,8 +859,10 @@ static int cortex_a8_debug_entry(struct target *target)
 	LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
 	/* REVISIT surely we should not re-read DSCR !! */
-	mem_ap_read_atomic_u32(swjdp,
+	retval = mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
 	 * imprecise data aborts get discarded by issuing a Data
@@ -816,6 +873,8 @@ static int cortex_a8_debug_entry(struct target *target)
 	dscr |= DSCR_ITR_EN;
 	retval = mem_ap_write_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DSCR, dscr);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* Examine debug reason */
 	arm_dpm_report_dscr(&armv7a->dpm, cortex_a8->cpudbg_dscr);
@@ -827,6 +886,8 @@ static int cortex_a8_debug_entry(struct target *target)
 		retval = mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_WFAR,
 				&wfar);
+		if (retval != ERROR_OK)
+			return retval;
 		arm_dpm_report_wfar(&armv7a->dpm, wfar);
 	}
 
@@ -951,6 +1012,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 	struct breakpoint *breakpoint = NULL;
 	struct breakpoint stepbreakpoint;
 	struct reg *r;
+	int retval;
 
 	int timeout = 100;
 
@@ -994,15 +1056,19 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 
 	target->debug_reason = DBG_REASON_SINGLESTEP;
 
-	cortex_a8_resume(target, 1, address, 0, 0);
+	retval = cortex_a8_resume(target, 1, address, 0, 0);
+	if (retval != ERROR_OK)
+		return retval;
 
 	while (target->state != TARGET_HALTED)
 	{
-		cortex_a8_poll(target);
+		retval = cortex_a8_poll(target);
+		if (retval != ERROR_OK)
+			return retval;
 		if (--timeout == 0)
 		{
-			LOG_WARNING("timeout waiting for target halt");
-			break;
+			LOG_ERROR("timeout waiting for target halt");
+			return ERROR_FAIL;
 		}
 	}
 
@@ -1035,7 +1101,7 @@ static int cortex_a8_restore_context(struct target *target, bool bpwp)
 
 
 /*
- * Cortex-A8 Breakpoint and watchpoint fuctions
+ * Cortex-A8 Breakpoint and watchpoint functions
  */
 
 /* Setup hardware Breakpoint Register Pair */
@@ -1195,7 +1261,7 @@ static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
 
 #if 0
-/* It is perfectly possible to remove brakpoints while the taget is running */
+/* It is perfectly possible to remove breakpoints while the target is running */
 	if (target->state != TARGET_HALTED)
 	{
 		LOG_WARNING("target not halted");
@@ -1217,7 +1283,7 @@ static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint
 
 
 /*
- * Cortex-A8 Reset fuctions
+ * Cortex-A8 Reset functions
  */
 
 static int cortex_a8_assert_reset(struct target *target)
@@ -1259,6 +1325,8 @@ static int cortex_a8_deassert_reset(struct target *target)
 	jtag_add_reset(0, 0);
 
 	retval = cortex_a8_poll(target);
+	if (retval != ERROR_OK)
+		return retval;
 
 	if (target->reset_halt) {
 		if (target->state != TARGET_HALTED) {
@@ -1313,12 +1381,16 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address,
 {
         int enabled = 0;
         uint32_t virt, phys;
+        int retval;
 
 	/* cortex_a8 handles unaligned memory access */
 
 // ???	dap_ap_select(swjdp, swjdp_memoryap);
         LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, size, count);
-        cortex_a8_mmu(target, &enabled);
+        retval = cortex_a8_mmu(target, &enabled);
+        if (retval != ERROR_OK)
+        	return retval;
+
         if(enabled)
         {
             virt = address;
@@ -1416,11 +1488,14 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address,
 {
         int enabled = 0;
         uint32_t virt, phys;
+        int retval;
 
 // ???  dap_ap_select(swjdp, swjdp_memoryap);
 
         LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, count);
-        cortex_a8_mmu(target, &enabled);
+        retval = cortex_a8_mmu(target, &enabled);
+        if (retval != ERROR_OK)
+        	return retval;
         if(enabled)
         {
             virt = address;
@@ -1728,7 +1803,7 @@ static uint32_t cortex_a8_get_ttb(struct target *target)
                     2, 0,   /* CRn, CRm */
                     &ttb);
     }
-    /* finaly we don't know whose ttb to use: user or kernel */
+    /* finally we don't know whose ttb to use: user or kernel */
     else
         LOG_ERROR("Don't know how to get ttb for current mode!!!");