X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_a8.c;h=90e1a00f08e6eac45c21940a2631244b1238675a;hb=b85dcae447581d06013cb7d68f582a8708c3cc50;hp=c39dba336621d36cb0288e1d8107a3492d0acc45;hpb=59bf45be1f37bd10c97bcfb1309f3c4c826b2a5a;p=openocd.git

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index c39dba3366..90e1a00f08 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -92,18 +92,25 @@ static int cortex_a8_init_debug_access(struct target *target)
 	{
 		/* try again */
 		retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
+		if (retval == ERROR_OK)
+		{
+			LOG_USER("Locking debug access failed on first, but succeeded on second try.");
+		}
 	}
 	if (retval != ERROR_OK)
 		return retval;
 	/* Clear Sticky Power Down status Bit in PRSR to enable access to
 	   the registers in the Core Power Domain */
 	retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
+	if (retval != ERROR_OK)
+		return retval;
+
 	/* Enabling of instruction execution in debug mode is done in debug_entry code */
 
 	/* Resync breakpoint registers */
 
-	/* Since this is likley called from init or reset, update targtet state information*/
-	cortex_a8_poll(target);
+	/* Since this is likely called from init or reset, update target state information*/
+	retval = cortex_a8_poll(target);
 
 	return retval;
 }
@@ -1005,6 +1012,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 	struct breakpoint *breakpoint = NULL;
 	struct breakpoint stepbreakpoint;
 	struct reg *r;
+	int retval;
 
 	int timeout = 100;
 
@@ -1048,15 +1056,19 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 
 	target->debug_reason = DBG_REASON_SINGLESTEP;
 
-	cortex_a8_resume(target, 1, address, 0, 0);
+	retval = cortex_a8_resume(target, 1, address, 0, 0);
+	if (retval != ERROR_OK)
+		return retval;
 
 	while (target->state != TARGET_HALTED)
 	{
-		cortex_a8_poll(target);
+		retval = cortex_a8_poll(target);
+		if (retval != ERROR_OK)
+			return retval;
 		if (--timeout == 0)
 		{
-			LOG_WARNING("timeout waiting for target halt");
-			break;
+			LOG_ERROR("timeout waiting for target halt");
+			return ERROR_FAIL;
 		}
 	}
 
@@ -1089,7 +1101,7 @@ static int cortex_a8_restore_context(struct target *target, bool bpwp)
 
 
 /*
- * Cortex-A8 Breakpoint and watchpoint fuctions
+ * Cortex-A8 Breakpoint and watchpoint functions
  */
 
 /* Setup hardware Breakpoint Register Pair */
@@ -1249,7 +1261,7 @@ static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
 
 #if 0
-/* It is perfectly possible to remove brakpoints while the taget is running */
+/* It is perfectly possible to remove breakpoints while the target is running */
 	if (target->state != TARGET_HALTED)
 	{
 		LOG_WARNING("target not halted");
@@ -1271,7 +1283,7 @@ static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint
 
 
 /*
- * Cortex-A8 Reset fuctions
+ * Cortex-A8 Reset functions
  */
 
 static int cortex_a8_assert_reset(struct target *target)
@@ -1313,6 +1325,8 @@ static int cortex_a8_deassert_reset(struct target *target)
 	jtag_add_reset(0, 0);
 
 	retval = cortex_a8_poll(target);
+	if (retval != ERROR_OK)
+		return retval;
 
 	if (target->reset_halt) {
 		if (target->state != TARGET_HALTED) {
@@ -1367,12 +1381,16 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address,
 {
         int enabled = 0;
         uint32_t virt, phys;
+        int retval;
 
 	/* cortex_a8 handles unaligned memory access */
 
 // ???	dap_ap_select(swjdp, swjdp_memoryap);
         LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, size, count);
-        cortex_a8_mmu(target, &enabled);
+        retval = cortex_a8_mmu(target, &enabled);
+        if (retval != ERROR_OK)
+        	return retval;
+
         if(enabled)
         {
             virt = address;
@@ -1470,11 +1488,14 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address,
 {
         int enabled = 0;
         uint32_t virt, phys;
+        int retval;
 
 // ???  dap_ap_select(swjdp, swjdp_memoryap);
 
         LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, count);
-        cortex_a8_mmu(target, &enabled);
+        retval = cortex_a8_mmu(target, &enabled);
+        if (retval != ERROR_OK)
+        	return retval;
         if(enabled)
         {
             virt = address;
@@ -1782,7 +1803,7 @@ static uint32_t cortex_a8_get_ttb(struct target *target)
                     2, 0,   /* CRn, CRm */
                     &ttb);
     }
-    /* finaly we don't know whose ttb to use: user or kernel */
+    /* finally we don't know whose ttb to use: user or kernel */
     else
         LOG_ERROR("Don't know how to get ttb for current mode!!!");