X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m.c;h=09a51b7b3b35f53996feaebe564f91d87e23ea60;hb=1b0c22dd5693233ac348d1f16aed18177e97c010;hp=625065c57957e876e9eecb8227b564b8f9771555;hpb=374127301ec1d72033b9d573b72c7abdfd61990d;p=openocd.git

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 625065c579..09a51b7b3b 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -31,6 +31,7 @@
 #include "config.h"
 #endif
 
+#include "jtag/interface.h"
 #include "breakpoints.h"
 #include "cortex_m.h"
 #include "target_request.h"
@@ -609,7 +610,7 @@ static int cortex_m3_halt(struct target *target)
 			return ERROR_TARGET_FAILURE;
 		} else {
 			/* we came here in a reset_halt or reset_init sequence
-			 * debug entry was already prepared in cortex_m3_prepare_reset_halt()
+			 * debug entry was already prepared in cortex_m3_assert_reset()
 			 */
 			target->debug_reason = DBG_REASON_DBGRQ;
 
@@ -995,10 +996,7 @@ static int cortex_m3_assert_reset(struct target *target)
 
 	if (jtag_reset_config & RESET_HAS_SRST) {
 		/* default to asserting srst */
-		if (jtag_reset_config & RESET_SRST_PULLS_TRST)
-			jtag_add_reset(1, 1);
-		else
-			jtag_add_reset(0, 1);
+		adapter_assert_reset();
 	} else {
 		/* Use a standard Cortex-M3 software reset mechanism.
 		 * We default to using VECRESET as it is supported on all current cores.
@@ -1051,7 +1049,7 @@ static int cortex_m3_deassert_reset(struct target *target)
 		target_state_name(target));
 
 	/* deassert reset lines */
-	jtag_add_reset(0, 0);
+	adapter_deassert_reset();
 
 	return ERROR_OK;
 }
@@ -1756,13 +1754,20 @@ fail1:
 	 */
 }
 
-static int cortex_m3_examine(struct target *target)
+#define MVFR0 0xe000ef40
+#define MVFR1 0xe000ef44
+
+#define MVFR0_DEFAULT_M4 0x10110021
+#define MVFR1_DEFAULT_M4 0x11000011
+
+int cortex_m3_examine(struct target *target)
 {
 	int retval;
-	uint32_t cpuid, fpcr;
+	uint32_t cpuid, fpcr, mvfr0, mvfr1;
 	int i;
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 	struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+	struct armv7m_common *armv7m = target_to_armv7m(target);
 
 	retval = ahbap_debugport_init(swjdp);
 	if (retval != ERROR_OK)
@@ -1776,11 +1781,24 @@ static int cortex_m3_examine(struct target *target)
 		if (retval != ERROR_OK)
 			return retval;
 
-		if (((cpuid >> 4) & 0xc3f) == 0xc23)
-			LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
-				(uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
+		/* Get CPU Type */
+		i = (cpuid >> 4) & 0xf;
+
+		LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
+				i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
 		LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
 
+		/* test for floating point feature on cortex-m4 */
+		if (i == 4) {
+			target_read_u32(target, MVFR0, &mvfr0);
+			target_read_u32(target, MVFR1, &mvfr1);
+
+			if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
+				LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
+				armv7m->fp_feature = FPv4_SP;
+			}
+		}
+
 		/* NOTE: FPB and DWT are both optional. */
 
 		/* Setup FPB */