X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m.c;h=62e08468dc2d9650c562cc9c5578efe1bec4497a;hb=6e339478999bab6ae029a3b24fa79ddc698e1a4f;hp=af245dfc0bf43f174acc920697ecb7f90c5828c6;hpb=17ac52360fc27eed9f58506a102a32b653d4d48c;p=openocd.git

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index af245dfc0b..62e08468dc 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -113,7 +113,7 @@ static int cortexm_dap_write_coreregister_u32(struct target *target,
 		return retval;
 
 	if (target->dbg_msg_enabled) {
-		/* restore DCB_DCRDR - this needs to be in a seperate
+		/* restore DCB_DCRDR - this needs to be in a separate
 		 * transaction otherwise the emulated DCC channel breaks */
 		if (retval == ERROR_OK)
 			retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
@@ -129,7 +129,7 @@ static int cortex_m_write_debug_halt_mask(struct target *target,
 	struct armv7m_common *armv7m = &cortex_m->armv7m;
 
 	/* mask off status bits */
-	cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
+	cortex_m->dcb_dhcsr &= ~((0xFFFFul << 16) | mask_off);
 	/* create new register mask */
 	cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 
@@ -445,6 +445,14 @@ static int cortex_m_examine_exception_reason(struct target *target)
 			if (retval != ERROR_OK)
 				return retval;
 			break;
+		case 7:	/* Secure Fault */
+			retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
+			if (retval != ERROR_OK)
+				return retval;
+			retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
+			if (retval != ERROR_OK)
+				return retval;
+			break;
 		case 11:	/* SVCall */
 			break;
 		case 12:	/* Debug Monitor */
@@ -951,7 +959,7 @@ static int cortex_m_step(struct target *target, int current,
 			 * just step over the instruction with interrupts disabled.
 			 *
 			 * The documentation has no information about this, it was found by observation
-			 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
+			 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
 			 * suffer from this problem.
 			 *
 			 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
@@ -966,8 +974,7 @@ static int cortex_m_step(struct target *target, int current,
 				/* Re-enable interrupts if appropriate */
 				cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 				cortex_m_set_maskints_for_halt(target);
-			}
-			else {
+			} else {
 
 				/* Set a temporary break point */
 				if (breakpoint) {
@@ -1980,7 +1987,7 @@ static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dw
 {
 	struct dwt_reg_state *state;
 
-	state = calloc(1, sizeof *state);
+	state = calloc(1, sizeof(*state));
 	if (!state)
 		return;
 	state->addr = d->addr;
@@ -2021,7 +2028,7 @@ fail0:
 		return;
 	}
 
-	cache = calloc(1, sizeof *cache);
+	cache = calloc(1, sizeof(*cache));
 	if (!cache) {
 fail1:
 		free(cm->dwt_comparator_list);
@@ -2029,7 +2036,7 @@ fail1:
 	}
 	cache->name = "Cortex-M DWT registers";
 	cache->num_regs = 2 + cm->dwt_num_comp * 3;
-	cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
+	cache->reg_list = calloc(cache->num_regs, sizeof(*cache->reg_list));
 	if (!cache->reg_list) {
 		free(cache);
 		goto fail1;
@@ -2231,6 +2238,19 @@ int cortex_m_examine(struct target *target)
 				armv7m->debug_ap->tar_autoincr_block = (1 << 10);
 		}
 
+		/* Enable debug requests */
+		retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
+		if (retval != ERROR_OK)
+			return retval;
+		if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
+			uint32_t dhcsr = (cortex_m->dcb_dhcsr | C_DEBUGEN) & ~(C_HALT | C_STEP | C_MASKINTS);
+
+			retval = target_write_u32(target, DCB_DHCSR, DBGKEY | (dhcsr & 0x0000FFFFUL));
+			if (retval != ERROR_OK)
+				return retval;
+			cortex_m->dcb_dhcsr = dhcsr;
+		}
+
 		/* Configure trace modules */
 		retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
 		if (retval != ERROR_OK)