X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m.c;h=62e08468dc2d9650c562cc9c5578efe1bec4497a;hb=6e339478999bab6ae029a3b24fa79ddc698e1a4f;hp=d9bee0e53d90d5fc3ee4be918fa57a09342a907d;hpb=37330f89d789e5b0a74aa14f7a7bfcfb4260abff;p=openocd.git

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index d9bee0e53d..62e08468dc 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -113,7 +113,7 @@ static int cortexm_dap_write_coreregister_u32(struct target *target,
 		return retval;
 
 	if (target->dbg_msg_enabled) {
-		/* restore DCB_DCRDR - this needs to be in a seperate
+		/* restore DCB_DCRDR - this needs to be in a separate
 		 * transaction otherwise the emulated DCC channel breaks */
 		if (retval == ERROR_OK)
 			retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
@@ -445,6 +445,14 @@ static int cortex_m_examine_exception_reason(struct target *target)
 			if (retval != ERROR_OK)
 				return retval;
 			break;
+		case 7:	/* Secure Fault */
+			retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
+			if (retval != ERROR_OK)
+				return retval;
+			retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
+			if (retval != ERROR_OK)
+				return retval;
+			break;
 		case 11:	/* SVCall */
 			break;
 		case 12:	/* Debug Monitor */
@@ -951,7 +959,7 @@ static int cortex_m_step(struct target *target, int current,
 			 * just step over the instruction with interrupts disabled.
 			 *
 			 * The documentation has no information about this, it was found by observation
-			 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
+			 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
 			 * suffer from this problem.
 			 *
 			 * To add some confusion: pc_value has bit 0 always set, while the breakpoint