X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m.c;h=b55de1bc6d67a450ef7594852c0fc9b031876f5d;hb=0663cb5e47413d42838fbbe15b568a20ee1c0232;hp=3e42af0a3d864ea4faeac75024368ae02d48d190;hpb=492bab62abe6e94a302899ed19af7e1b23365e78;p=openocd.git

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 3e42af0a3d..b55de1bc6d 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -1107,6 +1107,17 @@ static int cortex_m_deassert_reset(struct target *target)
 	/* deassert reset lines */
 	adapter_deassert_reset();
 
+	enum reset_types jtag_reset_config = jtag_get_reset_config();
+
+	if ((jtag_reset_config & RESET_HAS_SRST) &&
+	    !(jtag_reset_config & RESET_SRST_NO_GATING)) {
+		int retval = ahbap_debugport_init(target_to_cm(target)->armv7m.arm.dap);
+		if (retval != ERROR_OK) {
+			LOG_ERROR("DP initialisation failed");
+			return retval;
+		}
+	}
+
 	return ERROR_OK;
 }
 
@@ -1114,7 +1125,6 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
 {
 	int retval;
 	int fp_num = 0;
-	uint32_t hilo;
 	struct cortex_m_common *cortex_m = target_to_cm(target);
 	struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
 
@@ -1127,6 +1137,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
 		breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
 
 	if (breakpoint->type == BKPT_HARD) {
+		uint32_t fpcr_value;
 		while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
 			fp_num++;
 		if (fp_num >= cortex_m->fp_num_code) {
@@ -1134,9 +1145,17 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
 			return ERROR_FAIL;
 		}
 		breakpoint->set = fp_num + 1;
-		hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
+		fpcr_value = breakpoint->address | 1;
+		if (cortex_m->fp_rev == 0) {
+			uint32_t hilo;
+			hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
+			fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
+		} else if (cortex_m->fp_rev > 1) {
+			LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
+			return ERROR_FAIL;
+		}
 		comparator_list[fp_num].used = 1;
-		comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
+		comparator_list[fp_num].fpcr_value = fpcr_value;
 		target_write_u32(target, comparator_list[fp_num].fpcr_address,
 			comparator_list[fp_num].fpcr_value);
 		LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
@@ -1683,7 +1702,10 @@ void cortex_m_deinit_target(struct target *target)
 	struct cortex_m_common *cortex_m = target_to_cm(target);
 
 	free(cortex_m->fp_comparator_list);
+
 	cortex_m_dwt_free(target);
+	armv7m_free_reg_cache(target);
+
 	free(cortex_m);
 }
 
@@ -1913,10 +1935,14 @@ int cortex_m_examine(struct target *target)
 		    armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
 			/* free unavailable FPU registers */
 			size_t idx;
+
 			for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
 			     idx < armv7m->arm.core_cache->num_regs;
-			     idx++)
+			     idx++) {
 				free(armv7m->arm.core_cache->reg_list[idx].value);
+				free(armv7m->arm.core_cache->reg_list[idx].feature);
+				free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
+			}
 			armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
 		}
 
@@ -1944,6 +1970,9 @@ int cortex_m_examine(struct target *target)
 		cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
 		cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
 		cortex_m->fp_code_available = cortex_m->fp_num_code;
+		/* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
+		   Revision is zero base, fp_rev == 1 means Rev.2 ! */
+		cortex_m->fp_rev = (fpcr >> 28) & 0xf;
 		free(cortex_m->fp_comparator_list);
 		cortex_m->fp_comparator_list = calloc(
 				cortex_m->fp_num_code + cortex_m->fp_num_lit,