X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=6939890460895335e731b9a595505fbce97cad4e;hb=7dcde11b459f60d40db9ca53f038cd200c852064;hp=aecf371842beb3cfd55c8a67c4041345d0ea9505;hpb=8d13a4662647c33901592f699fcf544d88cfe443;p=openocd.git diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index aecf371842..6939890460 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -59,7 +59,7 @@ static void cortex_m3_enable_watchpoints(struct target *target); static int cortex_m3_store_core_reg_u32(struct target *target, enum armv7m_regtype type, uint32_t num, uint32_t value); -static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp, +static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp, uint32_t *value, int regnum) { int retval; @@ -68,17 +68,29 @@ static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp, /* because the DCB_DCRDR is used for the emulated dcc channel * we have to save/restore the DCB_DCRDR when used */ - mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); + retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); + if (retval != ERROR_OK) + return retval; /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */ - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); - dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum); + retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum); + if (retval != ERROR_OK) + return retval; /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */ - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); - dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); + retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); + if (retval != ERROR_OK) + return retval; - retval = jtagdp_transaction_endcheck(swjdp); + retval = dap_run(swjdp); + if (retval != ERROR_OK) + return retval; /* restore DCB_DCRDR - this needs to be in a seperate * transaction otherwise the emulated DCC channel breaks */ @@ -88,7 +100,7 @@ static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp, return retval; } -static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp, +static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp, uint32_t value, int regnum) { int retval; @@ -97,17 +109,25 @@ static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp, /* because the DCB_DCRDR is used for the emulated dcc channel * we have to save/restore the DCB_DCRDR when used */ - mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); + retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr); + if (retval != ERROR_OK) + return retval; /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */ - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); - dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); + retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value); + // XXX check retval /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */ - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); - dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR); + retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR); + // XXX check retval - retval = jtagdp_transaction_endcheck(swjdp); + retval = dap_run(swjdp); /* restore DCB_DCRDR - this needs to be in a seperate * transaction otherwise the emulated DCC channel breaks */ @@ -121,7 +141,7 @@ static int cortex_m3_write_debug_halt_mask(struct target *target, uint32_t mask_on, uint32_t mask_off) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info; + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; /* mask off status bits */ cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off); @@ -134,7 +154,7 @@ static int cortex_m3_write_debug_halt_mask(struct target *target, static int cortex_m3_clear_halt(struct target *target) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info; + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; /* clear step if any */ cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP); @@ -152,7 +172,7 @@ static int cortex_m3_clear_halt(struct target *target) static int cortex_m3_single_step_core(struct target *target) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info; + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; uint32_t dhcsr_save; /* backup dhcsr reg */ @@ -179,10 +199,11 @@ static int cortex_m3_single_step_core(struct target *target) static int cortex_m3_endreset_event(struct target *target) { int i; + int retval; uint32_t dcb_demcr; struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct armv7m_common *armv7m = &cortex_m3->armv7m; - struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info; + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list; struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list; @@ -234,14 +255,16 @@ static int cortex_m3_endreset_event(struct target *target) target_write_u32(target, dwt_list[i].dwt_comparator_address + 8, dwt_list[i].function); } - jtagdp_transaction_endcheck(swjdp); + retval = dap_run(swjdp); + if (retval != ERROR_OK) + return retval; register_cache_invalidate(cortex_m3->armv7m.core_cache); /* make sure we have latest dhcsr flags */ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); - return ERROR_OK; + return retval; } static int cortex_m3_examine_debug_reason(struct target *target) @@ -275,35 +298,54 @@ static int cortex_m3_examine_exception_reason(struct target *target) { uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1; struct armv7m_common *armv7m = target_to_armv7m(target); - struct swjdp_common *swjdp = &armv7m->swjdp_info; + struct adiv5_dap *swjdp = &armv7m->dap; + int retval; - mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr); + retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr); + if (retval != ERROR_OK) + return retval; switch (armv7m->exception_number) { case 2: /* NMI */ break; case 3: /* Hard Fault */ - mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr); + retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr); + if (retval != ERROR_OK) + return retval; if (except_sr & 0x40000000) { - mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr); + retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr); + if (retval != ERROR_OK) + return retval; } break; case 4: /* Memory Management */ - mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); - mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar); + retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar); + if (retval != ERROR_OK) + return retval; break; case 5: /* Bus Fault */ - mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); - mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar); + retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar); + if (retval != ERROR_OK) + return retval; break; case 6: /* Usage Fault */ - mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); + retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr); + if (retval != ERROR_OK) + return retval; break; case 11: /* SVCall */ break; case 12: /* Debug Monitor */ - mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr); + retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr); + if (retval != ERROR_OK) + return retval; break; case 14: /* PendSV */ break; @@ -313,10 +355,13 @@ static int cortex_m3_examine_exception_reason(struct target *target) except_sr = 0; break; } - jtagdp_transaction_endcheck(swjdp); - LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \ - shcsr, except_sr, cfsr, except_ar); - return ERROR_OK; + retval = dap_run(swjdp); + if (retval == ERROR_OK) + LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 + ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32, + armv7m_exception_string(armv7m->exception_number), + shcsr, except_sr, cfsr, except_ar); + return retval; } /* PSP is used in some thread modes */ @@ -345,7 +390,7 @@ static int cortex_m3_debug_entry(struct target *target) struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct armv7m_common *armv7m = &cortex_m3->armv7m; struct arm *arm = &armv7m->arm; - struct swjdp_common *swjdp = &armv7m->swjdp_info; + struct adiv5_dap *swjdp = &armv7m->dap; struct reg *r; LOG_DEBUG(" "); @@ -427,7 +472,11 @@ static int cortex_m3_debug_entry(struct target *target) target_state_name(target)); if (armv7m->post_debug_entry) - armv7m->post_debug_entry(target); + { + retval = armv7m->post_debug_entry(target); + if (retval != ERROR_OK) + return retval; + } return ERROR_OK; } @@ -437,7 +486,7 @@ static int cortex_m3_poll(struct target *target) int retval; enum target_state prev_target_state = target->state; struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info; + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; /* Read from Debug Halting Control and Status Register */ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -572,7 +621,7 @@ static int cortex_m3_halt(struct target *target) static int cortex_m3_soft_reset_halt(struct target *target) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info; + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; uint32_t dcb_dhcsr = 0; int retval, timeout = 0; @@ -746,7 +795,7 @@ static int cortex_m3_step(struct target *target, int current, { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct armv7m_common *armv7m = &cortex_m3->armv7m; - struct swjdp_common *swjdp = &armv7m->swjdp_info; + struct adiv5_dap *swjdp = &armv7m->dap; struct breakpoint *breakpoint = NULL; struct reg *pc = armv7m->arm.pc; bool bkpt_inst_found = false; @@ -798,7 +847,10 @@ static int cortex_m3_step(struct target *target, int current, " nvic_icsr = 0x%" PRIx32, cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr); - cortex_m3_debug_entry(target); + int retval; + retval = cortex_m3_debug_entry(target); + if (retval != ERROR_OK) + return retval; target_call_event_callbacks(target, TARGET_EVENT_HALTED); LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 @@ -811,7 +863,7 @@ static int cortex_m3_step(struct target *target, int current, static int cortex_m3_assert_reset(struct target *target) { struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info; + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; int assert_srst = 1; LOG_DEBUG("target->state: %s", @@ -1361,7 +1413,7 @@ static int cortex_m3_load_core_reg_u32(struct target *target, { int retval; struct armv7m_common *armv7m = target_to_armv7m(target); - struct swjdp_common *swjdp = &armv7m->swjdp_info; + struct adiv5_dap *swjdp = &armv7m->dap; /* NOTE: we "know" here that the register identifiers used * in the v7m header match the Cortex-M3 Debug Core Register @@ -1425,7 +1477,7 @@ static int cortex_m3_store_core_reg_u32(struct target *target, int retval; uint32_t reg; struct armv7m_common *armv7m = target_to_armv7m(target); - struct swjdp_common *swjdp = &armv7m->swjdp_info; + struct adiv5_dap *swjdp = &armv7m->dap; #ifdef ARMV7_GDB_HACKS /* If the LR register is being modified, make sure it will put us @@ -1503,7 +1555,7 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { struct armv7m_common *armv7m = target_to_armv7m(target); - struct swjdp_common *swjdp = &armv7m->swjdp_info; + struct adiv5_dap *swjdp = &armv7m->dap; int retval = ERROR_INVALID_ARGUMENTS; /* cortex_m3 handles unaligned memory access */ @@ -1528,7 +1580,7 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { struct armv7m_common *armv7m = target_to_armv7m(target); - struct swjdp_common *swjdp = &armv7m->swjdp_info; + struct adiv5_dap *swjdp = &armv7m->dap; int retval = ERROR_INVALID_ARGUMENTS; if (count && buffer) { @@ -1709,7 +1761,7 @@ static int cortex_m3_examine(struct target *target) uint32_t cpuid, fpcr; int i; struct cortex_m3_common *cortex_m3 = target_to_cm3(target); - struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info; + struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap; if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK) return retval; @@ -1758,7 +1810,7 @@ static int cortex_m3_examine(struct target *target) return ERROR_OK; } -static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl) +static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl) { uint16_t dcrdr; @@ -1783,7 +1835,7 @@ static int cortex_m3_target_request_data(struct target *target, uint32_t size, uint8_t *buffer) { struct armv7m_common *armv7m = target_to_armv7m(target); - struct swjdp_common *swjdp = &armv7m->swjdp_info; + struct adiv5_dap *swjdp = &armv7m->dap; uint8_t data; uint8_t ctrl; uint32_t i; @@ -1803,7 +1855,7 @@ static int cortex_m3_handle_target_request(void *priv) if (!target_was_examined(target)) return ERROR_OK; struct armv7m_common *armv7m = target_to_armv7m(target); - struct swjdp_common *swjdp = &armv7m->swjdp_info; + struct adiv5_dap *swjdp = &armv7m->dap; if (!target->dbg_msg_enabled) return ERROR_OK; @@ -1847,11 +1899,13 @@ static int cortex_m3_init_arch_info(struct target *target, cortex_m3->jtag_info.tap = tap; cortex_m3->jtag_info.scann_size = 4; + armv7m->arm.dap = &armv7m->dap; + /* Leave (only) generic DAP stuff for debugport_init(); */ - armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info; - armv7m->swjdp_info.memaccess_tck = 8; + armv7m->dap.jtag_info = &cortex_m3->jtag_info; + armv7m->dap.memaccess_tck = 8; /* Cortex-M3 has 4096 bytes autoincrement range */ - armv7m->swjdp_info.tar_autoincr_block = (1 << 12); + armv7m->dap.tar_autoincr_block = (1 << 12); /* register arch-specific functions */ armv7m->examine_debug_reason = cortex_m3_examine_debug_reason; @@ -1859,7 +1913,6 @@ static int cortex_m3_init_arch_info(struct target *target, armv7m->post_debug_entry = NULL; armv7m->pre_restore_context = NULL; - armv7m->post_restore_context = NULL; armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32; armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32; @@ -1921,7 +1974,7 @@ COMMAND_HANDLER(handle_cortex_m3_vector_catch_command) struct target *target = get_current_target(CMD_CTX); struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct armv7m_common *armv7m = &cortex_m3->armv7m; - struct swjdp_common *swjdp = &armv7m->swjdp_info; + struct adiv5_dap *swjdp = &armv7m->dap; uint32_t demcr = 0; int retval;