X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=93c88c0933c47c934e6aa19385edc629153642f8;hb=f0fac8a2cda054b0040ef2387d9c0776e06d73a7;hp=3011b59771652a061b1c58666628c569c6f72e80;hpb=81e0d4438ec4b4112e28a9e90ba2fc1fb548310b;p=openocd.git

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 3011b59771..93c88c0933 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -520,7 +520,8 @@ static int cortex_m3_debug_entry(struct target *target)
 
 static int cortex_m3_poll(struct target *target)
 {
-	int retval;
+	int detected_failure = ERROR_OK;
+	int retval = ERROR_OK;
 	enum target_state prev_target_state = target->state;
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 	struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
@@ -535,15 +536,18 @@ static int cortex_m3_poll(struct target *target)
 
 	/* Recover from lockup.  See ARMv7-M architecture spec,
 	 * section B1.5.15 "Unrecoverable exception cases".
-	 *
-	 * REVISIT Is there a better way to report and handle this?
 	 */
 	if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
-		LOG_WARNING("%s -- clearing lockup after double fault",
+		LOG_ERROR("%s -- clearing lockup after double fault",
 				target_name(target));
 		cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 		target->debug_reason = DBG_REASON_DBGRQ;
 
+		/* We have to execute the rest (the "finally" equivalent, but
+		 * still throw this exception again).
+		 */
+		detected_failure = ERROR_FAIL;
+
 		/* refresh status bits */
 		retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 		if (retval != ERROR_OK)
@@ -610,11 +614,14 @@ static int cortex_m3_poll(struct target *target)
 		if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
 		{
 			target->state = TARGET_RUNNING;
-			return ERROR_OK;
+			retval = ERROR_OK;
 		}
 	}
 
-	return ERROR_OK;
+	/* Did we detect a failure condition that we cleared? */
+	if (detected_failure != ERROR_OK)
+		retval = detected_failure;
+	return retval;
 }
 
 static int cortex_m3_halt(struct target *target)
@@ -920,16 +927,6 @@ static int cortex_m3_assert_reset(struct target *target)
 
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
 
-	/*
-	 * We can reset Cortex-M3 targets using just the NVIC without
-	 * requiring SRST, getting a SoC reset (or a core-only reset)
-	 * instead of a system reset.
-	 */
-	if (!(jtag_reset_config & RESET_HAS_SRST) &&
-			(cortex_m3->soft_reset_config == CORTEX_M3_RESET_SRST)) {
-		reset_config = CORTEX_M3_RESET_VECTRESET;
-	}
-
 	/* Enable debug requests */
 	int retval;
 	retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -977,7 +974,7 @@ static int cortex_m3_assert_reset(struct target *target)
 			return retval;
 	}
 
-	if (reset_config == CORTEX_M3_RESET_SRST)
+	if (jtag_reset_config & RESET_HAS_SRST)
 	{
 		/* default to asserting srst */
 		if (jtag_reset_config & RESET_SRST_PULLS_TRST)
@@ -1938,7 +1935,7 @@ static int cortex_m3_init_arch_info(struct target *target,
 
 	/* default reset mode is to use srst if fitted
 	 * if not it will use CORTEX_M3_RESET_VECTRESET */
-	cortex_m3->soft_reset_config = CORTEX_M3_RESET_SRST;
+	cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
 
 	armv7m->arm.dap = &armv7m->dap;
 
@@ -2127,20 +2124,14 @@ COMMAND_HANDLER(handle_cortex_m3_reset_config_command)
 
 	if (CMD_ARGC > 0)
 	{
-		if (strcmp(*CMD_ARGV, "systesetreq") == 0)
+		if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
 			cortex_m3->soft_reset_config = CORTEX_M3_RESET_SYSRESETREQ;
 		else if (strcmp(*CMD_ARGV, "vectreset") == 0)
 			cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
-		else
-			cortex_m3->soft_reset_config = CORTEX_M3_RESET_SRST;
 	}
 
 	switch (cortex_m3->soft_reset_config)
 	{
-		case CORTEX_M3_RESET_SRST:
-			reset_config = "srst";
-			break;
-
 		case CORTEX_M3_RESET_SYSRESETREQ:
 			reset_config = "sysresetreq";
 			break;