X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fdsp5680xx.h;h=9c8f435ce59caf2363c0338b459ae063eacd8237;hb=b9346fbd644253afe81e786b6649f000c4003214;hp=84e15998ac6010945fbbb812db7458d3ee4a1917;hpb=9d4aec6bda90ad39a140747ea270c6a09dd26440;p=openocd.git diff --git a/src/target/dsp5680xx.h b/src/target/dsp5680xx.h index 84e15998ac..9c8f435ce5 100644 --- a/src/target/dsp5680xx.h +++ b/src/target/dsp5680xx.h @@ -25,6 +25,19 @@ #include +/** + * @file dsp5680xx.h + * @author Rodrigo Rosa + * @date Thu Jun 9 18:54:38 2011 + * + * @brief Basic support for the 5680xx DSP from Freescale. + * The chip has two taps in the JTAG chain, the Master tap and the Core tap. + * In this code the Master tap is only used to unlock the flash memory by executing a JTAG instruction. + * + * + */ + + #define S_FILE_DATA_OFFSET 0x200000 //---------------------------------------------------------------- @@ -56,10 +69,10 @@ //---------------------------------------------------------------- // Master TAP instructions from MC56F8000RM.pdf //---------------------------------------------------------------- -#define MASTER_TAP_CMD_BYPASS 0xFF -#define MASTER_TAP_CMD_IDCODE 0x02 -#define MASTER_TAP_CMD_TLM_SEL 0x05 -#define MASTER_TAP_CMD_FLASH_ERASE 0x08 +#define MASTER_TAP_CMD_BYPASS 0xF +#define MASTER_TAP_CMD_IDCODE 0x2 +#define MASTER_TAP_CMD_TLM_SEL 0x5 +#define MASTER_TAP_CMD_FLASH_ERASE 0x8 //---------------------------------------------------------------- //---------------------------------------------------------------- @@ -114,16 +127,18 @@ #define DSP5680XX_ONCE_OPDBR 0x08 /* EOnCE Program Data Bus Register (OPDBR) */ #define DSP5680XX_ONCE_OTX1 0x09 /* EOnCE Upper Transmit register (OTX1) */ #define DSP5680XX_ONCE_OPABFR 0x0A /* OnCE Program Address Register—Fetch cycle */ -#define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */ +#define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */ #define DSP5680XX_ONCE_OCNTR_C 0x0C /* Clear OCNTR */ #define DSP5680XX_ONCE_ORX1 0x0D /* EOnCE Upper Receive register (ORX1) */ #define DSP5680XX_ONCE_OTBCR 0x0E /* EOnCE Trace Buffer Control Reg (OTBCR) */ #define DSP5680XX_ONCE_OPABER 0x10 /* OnCE Program Address Register—Execute cycle */ #define DSP5680XX_ONCE_OPFIFO 0x11 /* OnCE Program address FIFO */ -#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */ +#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */ #define DSP5680XX_ONCE_OPABDR 0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */ //---------------------------------------------------------------- +#define FLUSH_COUNT_READ_WRITE 8192 // This value works, higher values (and lower...) may work as well. +#define FLUSH_COUNT_FLASH 8192 //---------------------------------------------------------------- // HFM (flash module) Commands (ref:MC56F801xRM.pdf@159) //---------------------------------------------------------------- @@ -158,17 +173,25 @@ #define HFM_USTAT_MASK_BLANK 0x4 #define HFM_USTAT_MASK_PVIOL_ACCER 0x30 -#define HFM_CLK_DEFAULT 0x29 +/** + * The value used on for the FM clock is important to prevent flashing errors and to prevent deterioration of the FM. + * This value was calculated using a spreadsheet tool available on the Freescale website under FAQ 25464. + * + */ +#define HFM_CLK_DEFAULT 0x40 #define HFM_FLASH_BASE_ADDR 0x0 -#define HFM_SIZE 0x8000 // This is not true for 56F8013, but it is necessary to get the byte/word addressing workaround to actually work. -#define HFM_SIZE_REAL 0x2000 -#define HFM_SECTOR_SIZE 0x8000 // 512 bytes pages. -#define HFM_SECTOR_COUNT 1 +#define HFM_SIZE_BYTES 0x4000 // bytes +#define HFM_SIZE_WORDS 0x2000 // words +#define HFM_SECTOR_SIZE 0x200 // Size in bytes +#define HFM_SECTOR_COUNT 0x20 +// A 16K block in pages of 256 words. +/** + * Writing HFM_LOCK_FLASH to HFM_LOCK_ADDR_L and HFM_LOCK_ADDR_H will enable security on flash after the next reset. + */ #define HFM_LOCK_FLASH 0xE70A #define HFM_LOCK_ADDR_L 0x1FF7 #define HFM_LOCK_ADDR_H 0x1FF8 -// Writing HFM_LOCK_FLASH to HFM_LOCK_ADDR_L and HFM_LOCK_ADDR_H will enable security on flash after the next reset. //---------------------------------------------------------------- //---------------------------------------------------------------- @@ -176,7 +199,7 @@ //---------------------------------------------------------------- #define MC568013_EONCE_OBASE_ADDR 0xFF // The following are relative to EONCE_OBASE_ADDR (EONCE_OBASE_ADDR<<16 + ...) -#define MC568013_EONCE_TX_RX_ADDR 0xFFFE // +#define MC568013_EONCE_TX_RX_ADDR 0xFFFE // #define MC568013_EONCE_TX1_RX1_HIGH_ADDR 0xFFFF // Relative to EONCE_OBASE_ADDR #define MC568013_EONCE_OCR 0xFFA0 // Relative to EONCE_OBASE_ADDR //---------------------------------------------------------------- @@ -190,27 +213,117 @@ #define SIM_CMD_RESET 0x10 //---------------------------------------------------------------- -struct dsp5680xx_common -{ -//TODO +/** + * ---------------------------------------------------------------- + * ERROR codes - enable automatic parsing of output + * ---------------------------------------------------------------- + */ +#define DSP5680XX_ERROR_UNKNOWN_OR_ERROR_OPENOCD -100 +#define DSP5680XX_ERROR_JTAG_COMM -1 +#define DSP5680XX_ERROR_JTAG_RESET -2 +#define DSP5680XX_ERROR_JTAG_INVALID_TAP -3 +#define DSP5680XX_ERROR_JTAG_DR_LEN_OVERFLOW -4 +#define DSP5680XX_ERROR_INVALID_IR_LEN -5 +#define DSP5680XX_ERROR_JTAG_TAP_ENABLE_MASTER -6 +#define DSP5680XX_ERROR_JTAG_TAP_ENABLE_CORE -7 +#define DSP5680XX_ERROR_JTAG_TAP_FIND_MASTER -8 +#define DSP5680XX_ERROR_JTAG_TAP_FIND_CORE -9 +#define DSP5680XX_ERROR_JTAG_DRSCAN -10 +#define DSP5680XX_ERROR_JTAG_IRSCAN -11 +#define DSP5680XX_ERROR_ENTER_DEBUG_MODE -12 +#define DSP5680XX_ERROR_RESUME -13 +#define DSP5680XX_ERROR_WRITE_WITH_TARGET_RUNNING -14 +#define DSP5680XX_ERROR_INVALID_DATA_SIZE_UNIT -15 +#define DSP5680XX_ERROR_PROTECT_CHECK_INVALID_ARGS -16 +#define DSP5680XX_ERROR_FM_BUSY -17 +#define DSP5680XX_ERROR_FM_CMD_TIMED_OUT -18 +#define DSP5680XX_ERROR_FM_EXEC -19 +#define DSP5680XX_ERROR_FM_SET_CLK -20 +#define DSP5680XX_ERROR_FLASHING_INVALID_WORD_COUNT -21 +#define DSP5680XX_ERROR_FLASHING_CRC -22 +#define DSP5680XX_ERROR_FLASHING -23 +#define DSP5680XX_ERROR_NOT_IMPLEMENTED_STEP -24 +/** + * ---------------------------------------------------------------- + */ + +struct dsp5680xx_common{ + //TODO + uint32_t stored_pc; + int flush; }; -static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target *target) -{ - return target->arch_info; +extern struct dsp5680xx_common dsp5680xx_context; + +static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target *target){ + return target->arch_info; } -struct context -{ - uint32_t stored_pc; -}context; +/** + * Writes to flash memory. + * Does not check if flash is erased, it's up to the user to erase the flash before running this function. + * The flashing algorithm runs from RAM, reading from a register to which this function writes to. The algorithm is open loop, there is no control to verify that the FM read the register before writing the next data. A closed loop approach was much slower, and the current implementation does not fail, and if it did the crc check would detect it, allowing to flash again. + * + * @param target + * @param buffer + * @param address Word addressing. + * @param count In bytes. + * @param verify_flash Execute a CRC check after flashing. + * + * @return + */ +int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count, int is_flash_lock); -int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count); +/** + * The FM has the funcionality of checking if the flash array is erased. This function executes it. It does not support individual sector analysis. + * + * @param target + * @param erased + * @param sector This parameter is ignored because the FM does not support checking if individual sectors are erased. + * + * @return + */ +int dsp5680xx_f_erase_check(struct target * target,uint8_t * erased, uint32_t sector); -int dsp5680xx_f_erase_check(struct target * target,uint8_t * erased); +/** + * Erases either a sector or the complete flash array. If either the range first-last covers the complete array or if @first == 0 and @last == 0 then a mass erase command is executed on the FM. If not, then individual sectors are erased. + * + * @param target + * @param first + * @param last + * + * @return + */ int dsp5680xx_f_erase(struct target * target, int first, int last); -int dsp5680xx_f_protect_check(struct target * target, uint8_t * protected); + +/** + * Reads the memory mapped protection register. A 1 implies the sector is protected, a 0 implies the sector is not protected. + * + * @param target + * @param protected Data read from the protection register. + * + * @return + */ +int dsp5680xx_f_protect_check(struct target * target, uint16_t * protected); + +/** + * Writes the flash security words with a specific value. The chip's security will be enabled after the first reset following the execution of this function. + * + * @param target + * + * @return + */ int dsp5680xx_f_lock(struct target * target); + +/** + * Executes a mass erase command. The must be done from the Master tap. + * It is up to the user to select the master tap (jtag tapenable dsp5680xx.chp) before running this function. + * The flash array will be unsecured (and erased) after the first reset following the execution of this function. + * + * @param target + * + * @return + */ int dsp5680xx_f_unlock(struct target * target); #endif // dsp5680xx.h