X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.c;h=56368452a940203dca92d8fe8012e1e7a6194933;hb=e2b6de3d66bae70cb08fea17f5b66ee875dbb636;hp=e86a81cd43c5c5c131654df73f3b2c74e930cef9;hpb=20e4e77cdf366dedac21ff5670c54291feadfc05;p=openocd.git diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index e86a81cd43..56368452a9 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -2,6 +2,9 @@ * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * * * + * Copyright (C) 2007,2008 Øyvind Harboe * + * oyvind.harboe@zylin.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -88,6 +91,7 @@ int embeddedice_read_reg(reg_t *reg); reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9) { + int retval; reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t)); reg_t *reg_list = NULL; embeddedice_reg_t *arch_info = NULL; @@ -133,7 +137,16 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 /* identify EmbeddedICE version by reading DCC control register */ embeddedice_read_reg(®_list[EICE_COMMS_CTRL]); - jtag_execute_queue(); + if ((retval=jtag_execute_queue())!=ERROR_OK) + { + for (i = 0; i < num_regs; i++) + { + free(reg_list[i].value); + } + free(reg_list); + free(arch_info); + return NULL; + } eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4); @@ -149,7 +162,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 arm7_9->has_single_step = 1; break; case 3: - ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken"); + LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken"); reg_list[EICE_DBG_CTRL].size = 6; reg_list[EICE_DBG_STAT].size = 5; arm7_9->has_single_step = 1; @@ -172,38 +185,49 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7 arm7_9->has_monitor_mode = 1; break; case 7: - WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken"); + LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken"); reg_list[EICE_DBG_CTRL].size = 6; reg_list[EICE_DBG_STAT].size = 5; arm7_9->has_monitor_mode = 1; break; default: - ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32)); + LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32)); } + return reg_cache; +} + +int embeddedice_setup(target_t *target) +{ + int retval; + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + /* explicitly disable monitor mode */ if (arm7_9->has_monitor_mode) { - embeddedice_read_reg(®_list[EICE_DBG_CTRL]); - jtag_execute_queue(); - buf_set_u32(reg_list[EICE_DBG_CTRL].value, 4, 1, 0); - embeddedice_set_reg_w_exec(®_list[EICE_DBG_CTRL], reg_list[EICE_DBG_CTRL].value); + reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + + embeddedice_read_reg(dbg_ctrl); + if ((retval=jtag_execute_queue())!=ERROR_OK) + return retval; + buf_set_u32(dbg_ctrl->value, 4, 1, 0); + embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value); } - - return reg_cache; + return jtag_execute_queue(); } int embeddedice_get_reg(reg_t *reg) { if (embeddedice_read_reg(reg) != ERROR_OK) { - ERROR("BUG: error scheduling EmbeddedICE register read"); + LOG_ERROR("BUG: error scheduling EmbeddedICE register read"); exit(-1); } if (jtag_execute_queue() != ERROR_OK) { - ERROR("register read failed"); + LOG_ERROR("register read failed"); } return ERROR_OK; @@ -214,8 +238,8 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) embeddedice_reg_t *ice_reg = reg->arch_info; u8 reg_addr = ice_reg->addr & 0x1f; scan_field_t fields[3]; - - DEBUG("%i", ice_reg->addr); + u8 field1_out[1]; + u8 field2_out[1]; jtag_add_end_state(TAP_RTI); arm_jtag_scann(ice_reg->jtag_info, 0x2); @@ -234,7 +258,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) fields[1].device = ice_reg->jtag_info->chain_pos; fields[1].num_bits = 5; - fields[1].out_value = malloc(1); + fields[1].out_value = field1_out; buf_set_u32(fields[1].out_value, 0, 5, reg_addr); fields[1].out_mask = NULL; fields[1].in_value = NULL; @@ -245,7 +269,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) fields[2].device = ice_reg->jtag_info->chain_pos; fields[2].num_bits = 1; - fields[2].out_value = malloc(1); + fields[2].out_value = field2_out; buf_set_u32(fields[2].out_value, 0, 1, 0); fields[2].out_mask = NULL; fields[2].in_value = NULL; @@ -254,11 +278,10 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1, NULL); + jtag_add_dr_scan(3, fields, -1); fields[0].in_value = reg->value; - fields[0].in_check_value = check_value; - fields[0].in_check_mask = check_mask; + jtag_set_check_value(fields+0, check_value, check_mask, NULL); /* when reading the DCC data register, leaving the address field set to * EICE_COMMS_DATA would read the register twice @@ -266,11 +289,8 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) */ buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]); - jtag_add_dr_scan(3, fields, -1, NULL); + jtag_add_dr_scan(3, fields, -1); - free(fields[1].out_value); - free(fields[2].out_value); - return ERROR_OK; } @@ -280,9 +300,10 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) */ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) { - u8 reg_addr = 0x5; scan_field_t fields[3]; - + u8 field1_out[1]; + u8 field2_out[1]; + jtag_add_end_state(TAP_RTI); arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); @@ -299,8 +320,8 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) fields[1].device = jtag_info->chain_pos; fields[1].num_bits = 5; - fields[1].out_value = malloc(1); - buf_set_u32(fields[1].out_value, 0, 5, reg_addr); + fields[1].out_value = field1_out; + buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]); fields[1].out_mask = NULL; fields[1].in_value = NULL; fields[1].in_check_value = NULL; @@ -310,7 +331,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) fields[2].device = jtag_info->chain_pos; fields[2].num_bits = 1; - fields[2].out_value = malloc(1); + fields[2].out_value = field2_out; buf_set_u32(fields[2].out_value, 0, 1, 0); fields[2].out_mask = NULL; fields[2].in_value = NULL; @@ -319,7 +340,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, -1, NULL); + jtag_add_dr_scan(3, fields, -1); while (size > 0) { @@ -331,15 +352,12 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) fields[0].in_handler = arm_jtag_buf_to_u32; fields[0].in_handler_priv = data; - jtag_add_dr_scan(3, fields, -1, NULL); + jtag_add_dr_scan(3, fields, -1); data++; size--; } - free(fields[1].out_value); - free(fields[2].out_value); - return jtag_execute_queue(); } @@ -352,7 +370,7 @@ int embeddedice_set_reg(reg_t *reg, u32 value) { if (embeddedice_write_reg(reg, value) != ERROR_OK) { - ERROR("BUG: error scheduling EmbeddedICE register write"); + LOG_ERROR("BUG: error scheduling EmbeddedICE register write"); exit(-1); } @@ -369,7 +387,7 @@ int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf) if (jtag_execute_queue() != ERROR_OK) { - ERROR("register write failed"); + LOG_ERROR("register write failed"); exit(-1); } return ERROR_OK; @@ -378,31 +396,54 @@ int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf) int embeddedice_write_reg(reg_t *reg, u32 value) { embeddedice_reg_t *ice_reg = reg->arch_info; - u8 reg_addr = ice_reg->addr & 0x1f; - scan_field_t fields[3]; - - DEBUG("%i: 0x%8.8x", ice_reg->addr, value); + + LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value); jtag_add_end_state(TAP_RTI); arm_jtag_scann(ice_reg->jtag_info, 0x2); arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); + + u8 reg_addr = ice_reg->addr & 0x1f; + embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value); - fields[0].device = ice_reg->jtag_info->chain_pos; + return ERROR_OK; +} + +int embeddedice_store_reg(reg_t *reg) +{ + return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size)); +} + +/* send words of 32 bit to the DCC + * we pretend the target is always going to be fast enough + * (relative to the JTAG clock), so we don't need to handshake + */ +int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size) +{ + scan_field_t fields[3]; + u8 field0_out[4]; + u8 field1_out[1]; + u8 field2_out[1]; + + jtag_add_end_state(TAP_RTI); + arm_jtag_scann(jtag_info, 0x2); + arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + + fields[0].device = jtag_info->chain_pos; fields[0].num_bits = 32; - fields[0].out_value = malloc(4); - buf_set_u32(fields[0].out_value, 0, 32, value); + fields[0].out_value = field0_out; fields[0].out_mask = NULL; fields[0].in_value = NULL; fields[0].in_check_value = NULL; fields[0].in_check_mask = NULL; fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - - fields[1].device = ice_reg->jtag_info->chain_pos; + + fields[1].device = jtag_info->chain_pos; fields[1].num_bits = 5; - fields[1].out_value = malloc(1); - buf_set_u32(fields[1].out_value, 0, 5, reg_addr); + fields[1].out_value = field1_out; + buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]); fields[1].out_mask = NULL; fields[1].in_value = NULL; fields[1].in_check_value = NULL; @@ -410,9 +451,9 @@ int embeddedice_write_reg(reg_t *reg, u32 value) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - fields[2].device = ice_reg->jtag_info->chain_pos; + fields[2].device = jtag_info->chain_pos; fields[2].num_bits = 1; - fields[2].out_value = malloc(1); + fields[2].out_value = field2_out; buf_set_u32(fields[2].out_value, 0, 1, 1); fields[2].out_mask = NULL; fields[2].in_value = NULL; @@ -420,18 +461,90 @@ int embeddedice_write_reg(reg_t *reg, u32 value) fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - - jtag_add_dr_scan(3, fields, -1, NULL); - - free(fields[0].out_value); - free(fields[1].out_value); - free(fields[2].out_value); - + + while (size > 0) + { + buf_set_u32(fields[0].out_value, 0, 32, *data); + jtag_add_dr_scan(3, fields, -1); + + data++; + size--; + } + + /* call to jtag_execute_queue() intentionally omitted */ return ERROR_OK; } -int embeddedice_store_reg(reg_t *reg) +/* wait for DCC control register R/W handshake bit to become active + */ +int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) { - return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size)); -} + scan_field_t fields[3]; + u8 field0_in[4]; + u8 field1_out[1]; + u8 field2_out[1]; + int retval; + int hsact; + struct timeval lap; + struct timeval now; + + if (hsbit == EICE_COMM_CTRL_WBIT) + hsact = 1; + else if (hsbit == EICE_COMM_CTRL_RBIT) + hsact = 0; + else + return ERROR_INVALID_ARGUMENTS; + + jtag_add_end_state(TAP_RTI); + arm_jtag_scann(jtag_info, 0x2); + arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + + fields[0].device = jtag_info->chain_pos; + fields[0].num_bits = 32; + fields[0].out_value = NULL; + fields[0].out_mask = NULL; + fields[0].in_value = field0_in; + fields[0].in_check_value = NULL; + fields[0].in_check_mask = NULL; + fields[0].in_handler = NULL; + fields[0].in_handler_priv = NULL; + + fields[1].device = jtag_info->chain_pos; + fields[1].num_bits = 5; + fields[1].out_value = field1_out; + buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]); + fields[1].out_mask = NULL; + fields[1].in_value = NULL; + fields[1].in_check_value = NULL; + fields[1].in_check_mask = NULL; + fields[1].in_handler = NULL; + fields[1].in_handler_priv = NULL; + fields[2].device = jtag_info->chain_pos; + fields[2].num_bits = 1; + fields[2].out_value = field2_out; + buf_set_u32(fields[2].out_value, 0, 1, 0); + fields[2].out_mask = NULL; + fields[2].in_value = NULL; + fields[2].in_check_value = NULL; + fields[2].in_check_mask = NULL; + fields[2].in_handler = NULL; + fields[2].in_handler_priv = NULL; + + jtag_add_dr_scan(3, fields, -1); + gettimeofday(&lap, NULL); + do + { + jtag_add_dr_scan(3, fields, -1); + if ((retval = jtag_execute_queue()) != ERROR_OK) + return retval; + + if (buf_get_u32(field0_in, hsbit, 1) == hsact) + return ERROR_OK; + + gettimeofday(&now, NULL); + } + while ((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000 <= timeout); + + return ERROR_TARGET_TIMEOUT; +}