X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.c;h=7aef153b584dfabe6d9af984e34a64e6062c5484;hb=HEAD;hp=3f0048e4d4c1c21a663afe52a35edcb7d6962cf6;hpb=056fcdb540f0ab9a404f3b5de72fd707eb146603;p=openocd.git diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 3f0048e4d4..7aef153b58 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -1,42 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * * * - * Copyright (C) 2007,2008,2009 Øyvind Harboe * + * Copyright (C) 2007-2010 Øyvind Harboe * * oyvind.harboe@zylin.com * * * * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "embeddedice.h" - -#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0]))) +#include "register.h" +#include /** * @file * * This provides lowlevel glue to the EmbeddedICE (or EmbeddedICE-RT) * module found on scan chain 2 in ARM7, ARM9, and some other families - * of ARM cores. + * of ARM cores. The module is called "EmbeddedICE-RT" if it has + * monitor mode support. * * EmbeddedICE provides basic watchpoint/breakpoint hardware and a Debug * Communications Channel (DCC) used to read or write 32-bit words to @@ -47,13 +36,15 @@ * core entered debug mode. */ +static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf); + /* * From: ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores) */ static const struct { - char *name; - unsigned short addr; - unsigned short width; + const char *name; + unsigned short addr; + unsigned short width; } eice_regs[] = { [EICE_DBG_CTRL] = { .name = "debug_ctrl", @@ -85,7 +76,7 @@ static const struct { .addr = 9, .width = 32, }, - [EICE_W0_DATA_VALUE ] = { + [EICE_W0_DATA_VALUE] = { .name = "watch_0_data_value", .addr = 10, .width = 32, @@ -143,50 +134,50 @@ static const struct { }, }; - -static int embeddedice_reg_arch_type = -1; - -static int embeddedice_get_reg(reg_t *reg) +static int embeddedice_get_reg(struct reg *reg) { - int retval; - - if ((retval = embeddedice_read_reg(reg)) != ERROR_OK) + int retval = embeddedice_read_reg(reg); + if (retval != ERROR_OK) { LOG_ERROR("error queueing EmbeddedICE register read"); - else if ((retval = jtag_execute_queue()) != ERROR_OK) + return retval; + } + + retval = jtag_execute_queue(); + if (retval != ERROR_OK) LOG_ERROR("EmbeddedICE register read failed"); return retval; } +static const struct reg_arch_type eice_reg_type = { + .get = embeddedice_get_reg, + .set = embeddedice_set_reg_w_exec, +}; + /** * Probe EmbeddedICE module and set up local records of its registers. * Different versions of the modules have different capabilities, such as * hardware support for vector_catch, single stepping, and monitor mode. */ -reg_cache_t * -embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9) +struct reg_cache *embeddedice_build_reg_cache(struct target *target, + struct arm7_9_common *arm7_9) { int retval; - reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t)); - reg_t *reg_list = NULL; - embeddedice_reg_t *arch_info = NULL; + struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache)); + struct reg *reg_list = NULL; + struct embeddedice_reg *arch_info = NULL; struct arm_jtag *jtag_info = &arm7_9->jtag_info; int num_regs = ARRAY_SIZE(eice_regs); int i; int eice_version = 0; - /* register arch-type for EmbeddedICE registers only once */ - if (embeddedice_reg_arch_type == -1) - embeddedice_reg_arch_type = register_reg_arch_type( - embeddedice_get_reg, embeddedice_set_reg_w_exec); - /* vector_catch isn't always present */ if (!arm7_9->has_vector_catch) num_regs--; /* the actual registers are kept in two arrays */ - reg_list = calloc(num_regs, sizeof(reg_t)); - arch_info = calloc(num_regs, sizeof(embeddedice_reg_t)); + reg_list = calloc(num_regs, sizeof(struct reg)); + arch_info = calloc(num_regs, sizeof(struct embeddedice_reg)); /* fill in values for the reg cache */ reg_cache->name = "EmbeddedICE registers"; @@ -194,30 +185,30 @@ embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9) reg_cache->reg_list = reg_list; reg_cache->num_regs = num_regs; + /* FIXME the second watchpoint unit on Feroceon and Dragonite + * seems not to work ... we should have a way to not set up + * its four registers here! + */ + /* set up registers */ - for (i = 0; i < num_regs; i++) - { + for (i = 0; i < num_regs; i++) { reg_list[i].name = eice_regs[i].name; reg_list[i].size = eice_regs[i].width; - reg_list[i].dirty = 0; - reg_list[i].valid = 0; - reg_list[i].bitfield_desc = NULL; - reg_list[i].num_bitfields = 0; + reg_list[i].dirty = false; + reg_list[i].valid = false; reg_list[i].value = calloc(1, 4); reg_list[i].arch_info = &arch_info[i]; - reg_list[i].arch_type = embeddedice_reg_arch_type; + reg_list[i].type = &eice_reg_type; arch_info[i].addr = eice_regs[i].addr; arch_info[i].jtag_info = jtag_info; } /* identify EmbeddedICE version by reading DCC control register */ embeddedice_read_reg(®_list[EICE_COMMS_CTRL]); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) { for (i = 0; i < num_regs; i++) - { free(reg_list[i].value); - } free(reg_list); free(reg_cache); free(arch_info); @@ -227,8 +218,7 @@ embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9) eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4); LOG_INFO("Embedded ICE version %d", eice_version); - switch (eice_version) - { + switch (eice_version) { case 1: /* ARM7TDMI r3, ARM7TDMI-S r3 * @@ -286,21 +276,42 @@ embeddedice_build_reg_cache(target_t *target, struct arm7_9_common *arm7_9) * in some unusual bits. Let feroceon.c validate it * and do the appropriate setup itself. */ - if (strcmp(target_get_name(target), "feroceon") == 0 || - strcmp(target_get_name(target), "dragonite") == 0) + if (strcmp(target_type_name(target), "feroceon") == 0 || + strcmp(target_type_name(target), "dragonite") == 0) break; LOG_ERROR("unknown EmbeddedICE version " "(comms ctrl: 0x%8.8" PRIx32 ")", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32)); } + /* On Feroceon and Dragonite the second unit is seemingly missing. */ + LOG_INFO("%s: hardware has %d breakpoint/watchpoint unit%s", + target_name(target), arm7_9->wp_available_max, + (arm7_9->wp_available_max != 1) ? "s" : ""); + return reg_cache; } +/** + * Free all memory allocated for EmbeddedICE register cache + */ +void embeddedice_free_reg_cache(struct reg_cache *reg_cache) +{ + if (!reg_cache) + return; + + for (unsigned int i = 0; i < reg_cache->num_regs; i++) + free(reg_cache->reg_list[i].value); + + free(reg_cache->reg_list[0].arch_info); + free(reg_cache->reg_list); + free(reg_cache); +} + /** * Initialize EmbeddedICE module, if needed. */ -int embeddedice_setup(target_t *target) +int embeddedice_setup(struct target *target) { int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -310,12 +321,12 @@ int embeddedice_setup(target_t *target) * that manages break requests. ARM's "Angel Debug Monitor" is one * common example of such code. */ - if (arm7_9->has_monitor_mode) - { - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + if (arm7_9->has_monitor_mode) { + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; embeddedice_read_reg(dbg_ctrl); - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; buf_set_u32(dbg_ctrl->value, 4, 1, 0); embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value); @@ -328,22 +339,26 @@ int embeddedice_setup(target_t *target) * optionally checking the value read. * Note that at this level, all registers are 32 bits wide. */ -int embeddedice_read_reg_w_check(reg_t *reg, +int embeddedice_read_reg_w_check(struct reg *reg, uint8_t *check_value, uint8_t *check_mask) { - embeddedice_reg_t *ice_reg = reg->arch_info; + struct embeddedice_reg *ice_reg = reg->arch_info; uint8_t reg_addr = ice_reg->addr & 0x1f; struct scan_field fields[3]; uint8_t field1_out[1]; uint8_t field2_out[1]; + int retval; - jtag_set_end_state(TAP_IDLE); - arm_jtag_scann(ice_reg->jtag_info, 0x2); + retval = arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE); + if (retval != ERROR_OK) + return retval; - arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); + retval = arm_jtag_set_instr(ice_reg->jtag_info->tap, + ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; /* bits 31:0 -- data (ignored here) */ - fields[0].tap = ice_reg->jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = reg->value; fields[0].in_value = NULL; @@ -351,25 +366,23 @@ int embeddedice_read_reg_w_check(reg_t *reg, fields[0].check_mask = NULL; /* bits 36:32 -- register */ - fields[1].tap = ice_reg->jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, reg_addr); + field1_out[0] = reg_addr; fields[1].in_value = NULL; fields[1].check_value = NULL; fields[1].check_mask = NULL; /* bit 37 -- 0/read */ - fields[2].tap = ice_reg->jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 0); + field2_out[0] = 0; fields[2].in_value = NULL; fields[2].check_value = NULL; fields[2].check_mask = NULL; /* traverse Update-DR, setting address for the next read */ - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(ice_reg->jtag_info->tap, 3, fields, TAP_IDLE); /* bits 31:0 -- the data we're reading (and maybe checking) */ fields[0].in_value = reg->value; @@ -380,10 +393,10 @@ int embeddedice_read_reg_w_check(reg_t *reg, * EICE_COMMS_DATA would read the register twice * reading the control register is safe */ - buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_CTRL].addr); + field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr; /* traverse Update-DR, reading but with no other side effects */ - jtag_add_dr_scan_check(3, fields, jtag_get_end_state()); + jtag_add_dr_scan_check(ice_reg->jtag_info->tap, 3, fields, TAP_IDLE); return ERROR_OK; } @@ -401,41 +414,40 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz struct scan_field fields[3]; uint8_t field1_out[1]; uint8_t field2_out[1]; + int retval; - jtag_set_end_state(TAP_IDLE); - arm_jtag_scann(jtag_info, 0x2); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; - fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].in_value = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr); + field1_out[0] = eice_regs[EICE_COMMS_DATA].addr; fields[1].in_value = NULL; - fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 0); + field2_out[0] = 0; fields[2].in_value = NULL; - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE); - while (size > 0) - { + while (size > 0) { /* when reading the last item, set the register address to the DCC control reg, * to avoid reading additional data from the DCC data reg */ if (size == 1) - buf_set_u32(fields[1].out_value, 0, 5, - eice_regs[EICE_COMMS_CTRL].addr); + field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr; fields[0].in_value = (uint8_t *)data; - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE); jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)data); data++; @@ -449,7 +461,7 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz * Queue a read for an EmbeddedICE register into the register cache, * not checking the value read. */ -int embeddedice_read_reg(reg_t *reg) +int embeddedice_read_reg(struct reg *reg) { return embeddedice_read_reg_w_check(reg, NULL, NULL); } @@ -458,13 +470,13 @@ int embeddedice_read_reg(reg_t *reg) * Queue a write for an EmbeddedICE register, updating the register cache. * Uses embeddedice_write_reg(). */ -void embeddedice_set_reg(reg_t *reg, uint32_t value) +void embeddedice_set_reg(struct reg *reg, uint32_t value) { embeddedice_write_reg(reg, value); buf_set_u32(reg->value, 0, reg->size, value); - reg->valid = 1; - reg->dirty = 0; + reg->valid = true; + reg->dirty = false; } @@ -472,12 +484,13 @@ void embeddedice_set_reg(reg_t *reg, uint32_t value) * Write an EmbeddedICE register, updating the register cache. * Uses embeddedice_set_reg(); not queued. */ -int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf) +static int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf) { int retval; embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size)); - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) LOG_ERROR("register write failed"); return retval; } @@ -485,16 +498,15 @@ int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf) /** * Queue a write for an EmbeddedICE register, bypassing the register cache. */ -void embeddedice_write_reg(reg_t *reg, uint32_t value) +void embeddedice_write_reg(struct reg *reg, uint32_t value) { - embeddedice_reg_t *ice_reg = reg->arch_info; + struct embeddedice_reg *ice_reg = reg->arch_info; LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value); - jtag_set_end_state(TAP_IDLE); - arm_jtag_scann(ice_reg->jtag_info, 0x2); + arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE); - arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); + arm_jtag_set_instr(ice_reg->jtag_info->tap, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE); uint8_t reg_addr = ice_reg->addr & 0x1f; embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value); @@ -504,7 +516,7 @@ void embeddedice_write_reg(reg_t *reg, uint32_t value) * Queue a write for an EmbeddedICE register, using cached value. * Uses embeddedice_write_reg(). */ -void embeddedice_store_reg(reg_t *reg) +void embeddedice_store_reg(struct reg *reg) { embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size)); } @@ -523,33 +535,33 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size) uint8_t field0_out[4]; uint8_t field1_out[1]; uint8_t field2_out[1]; + int retval; - jtag_set_end_state(TAP_IDLE); - arm_jtag_scann(jtag_info, 0x2); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; - fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = field0_out; fields[0].in_value = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr); + field1_out[0] = eice_regs[EICE_COMMS_DATA].addr; fields[1].in_value = NULL; - fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 1); + field2_out[0] = 1; fields[2].in_value = NULL; - while (size > 0) - { - buf_set_u32(fields[0].out_value, 0, 32, *data); - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + while (size > 0) { + buf_set_u32(field0_out, 0, 32, *data); + jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE); data++; size--; @@ -570,70 +582,69 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou uint8_t field2_out[1]; int retval; uint32_t hsact; - struct timeval lap; struct timeval now; + struct timeval timeout_end; if (hsbit == EICE_COMM_CTRL_WBIT) hsact = 1; else if (hsbit == EICE_COMM_CTRL_RBIT) hsact = 0; - else - return ERROR_INVALID_ARGUMENTS; + else { + LOG_ERROR("Invalid arguments"); + return ERROR_COMMAND_SYNTAX_ERROR; + } - jtag_set_end_state(TAP_IDLE); - arm_jtag_scann(jtag_info, 0x2); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + retval = arm_jtag_scann(jtag_info, 0x2, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; - fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].in_value = field0_in; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 5; fields[1].out_value = field1_out; - buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr); + field1_out[0] = eice_regs[EICE_COMMS_DATA].addr; fields[1].in_value = NULL; - fields[2].tap = jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = field2_out; - buf_set_u32(fields[2].out_value, 0, 1, 0); + field2_out[0] = 0; fields[2].in_value = NULL; - jtag_add_dr_scan(3, fields, jtag_get_end_state()); - gettimeofday(&lap, NULL); + jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE); + gettimeofday(&timeout_end, NULL); + timeval_add_time(&timeout_end, 0, timeout * 1000); do { - jtag_add_dr_scan(3, fields, jtag_get_end_state()); - if ((retval = jtag_execute_queue()) != ERROR_OK) + jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; if (buf_get_u32(field0_in, hsbit, 1) == hsact) return ERROR_OK; gettimeofday(&now, NULL); - } while ((uint32_t)((now.tv_sec - lap.tv_sec) * 1000 - + (now.tv_usec - lap.tv_usec) / 1000) <= timeout); + } while (timeval_compare(&now, &timeout_end) <= 0); + LOG_ERROR("embeddedice handshake timeout"); return ERROR_TARGET_TIMEOUT; } -#ifndef HAVE_JTAG_MINIDRIVER_H /** * This is an inner loop of the open loop DCC write of data to target */ void embeddedice_write_dcc(struct jtag_tap *tap, - int reg_addr, uint8_t *buffer, int little, int count) + int reg_addr, const uint8_t *buffer, int little, int count) { int i; - for (i = 0; i < count; i++) - { + for (i = 0; i < count; i++) { embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little)); buffer += 4; } } -#else -/* provided by minidriver */ -#endif