X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fetb.c;h=1315b71a12439e69bbe92ceb27dfb15113f20ae2;hb=248448ee3a5f4f97307f1d5af4ef940529478a34;hp=0e16b22bdecf3c62a43836040bc8e2db9d7ca68d;hpb=f90d8fa45f2d4c9d4b7990f198b232ee55cbb4e1;p=openocd.git diff --git a/src/target/etb.c b/src/target/etb.c index 0e16b22bde..1315b71a12 100644 --- a/src/target/etb.c +++ b/src/target/etb.c @@ -21,7 +21,7 @@ #include "config.h" #endif -#include "arm7_9_common.h" +#include "armv4_5.h" #include "etb.h" @@ -42,11 +42,9 @@ static int etb_reg_arch_type = -1; static int etb_get_reg(reg_t *reg); -static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); - static int etb_set_instr(etb_t *etb, uint32_t new_instr) { - jtag_tap_t *tap; + struct jtag_tap *tap; tap = etb->tap; if (tap == NULL) @@ -54,7 +52,7 @@ static int etb_set_instr(etb_t *etb, uint32_t new_instr) if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) { - scan_field_t field; + struct scan_field field; field.tap = tap; field.num_bits = tap->ir_length; @@ -75,7 +73,7 @@ static int etb_scann(etb_t *etb, uint32_t new_scan_chain) { if (etb->cur_scan_chain != new_scan_chain) { - scan_field_t field; + struct scan_field field; field.tap = etb->tap; field.num_bits = 5; @@ -96,6 +94,33 @@ static int etb_scann(etb_t *etb, uint32_t new_scan_chain) return ERROR_OK; } +static int etb_read_reg_w_check(reg_t *, uint8_t *, uint8_t *); +static int etb_set_reg_w_exec(reg_t *, uint8_t *); + +static int etb_read_reg(reg_t *reg) +{ + return etb_read_reg_w_check(reg, NULL, NULL); +} + +static int etb_get_reg(reg_t *reg) +{ + int retval; + + if ((retval = etb_read_reg(reg)) != ERROR_OK) + { + LOG_ERROR("BUG: error scheduling ETB register read"); + return retval; + } + + if ((retval = jtag_execute_queue()) != ERROR_OK) + { + LOG_ERROR("ETB register read failed"); + return retval; + } + + return ERROR_OK; +} + reg_cache_t* etb_build_reg_cache(etb_t *etb) { reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t)); @@ -138,36 +163,17 @@ reg_cache_t* etb_build_reg_cache(etb_t *etb) return reg_cache; } -static int etb_get_reg(reg_t *reg) -{ - int retval; - - if ((retval = etb_read_reg(reg)) != ERROR_OK) - { - LOG_ERROR("BUG: error scheduling etm register read"); - return retval; - } - - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - LOG_ERROR("register read failed"); - return retval; - } - - return ERROR_OK; -} - - static void etb_getbuf(jtag_callback_data_t arg) { - uint8_t *in = (uint8_t *)arg; + uint8_t *in = (uint8_t *)arg; + *((uint32_t *)in) = buf_get_u32(in, 0, 32); } static int etb_read_ram(etb_t *etb, uint32_t *data, int num_frames) { - scan_field_t fields[3]; + struct scan_field fields[3]; int i; jtag_set_end_state(TAP_IDLE); @@ -218,11 +224,12 @@ static int etb_read_ram(etb_t *etb, uint32_t *data, int num_frames) return ERROR_OK; } -int etb_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask) +static int etb_read_reg_w_check(reg_t *reg, + uint8_t* check_value, uint8_t* check_mask) { etb_reg_t *etb_reg = reg->arch_info; uint8_t reg_addr = etb_reg->addr & 0x7f; - scan_field_t fields[3]; + struct scan_field fields[3]; LOG_DEBUG("%i", (int)(etb_reg->addr)); @@ -271,18 +278,15 @@ int etb_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask) return ERROR_OK; } -int etb_read_reg(reg_t *reg) -{ - return etb_read_reg_w_check(reg, NULL, NULL); -} +static int etb_write_reg(reg_t *, uint32_t); -int etb_set_reg(reg_t *reg, uint32_t value) +static int etb_set_reg(reg_t *reg, uint32_t value) { int retval; if ((retval = etb_write_reg(reg, value)) != ERROR_OK) { - LOG_ERROR("BUG: error scheduling etm register write"); + LOG_ERROR("BUG: error scheduling ETB register write"); return retval; } @@ -293,7 +297,7 @@ int etb_set_reg(reg_t *reg, uint32_t value) return ERROR_OK; } -int etb_set_reg_w_exec(reg_t *reg, uint8_t *buf) +static int etb_set_reg_w_exec(reg_t *reg, uint8_t *buf) { int retval; @@ -301,17 +305,17 @@ int etb_set_reg_w_exec(reg_t *reg, uint8_t *buf) if ((retval = jtag_execute_queue()) != ERROR_OK) { - LOG_ERROR("register write failed"); + LOG_ERROR("ETB: register write failed"); return retval; } return ERROR_OK; } -int etb_write_reg(reg_t *reg, uint32_t value) +static int etb_write_reg(reg_t *reg, uint32_t value) { etb_reg_t *etb_reg = reg->arch_info; uint8_t reg_addr = etb_reg->addr & 0x7f; - scan_field_t fields[3]; + struct scan_field fields[3]; LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value); @@ -345,28 +349,11 @@ int etb_write_reg(reg_t *reg, uint32_t value) return ERROR_OK; } -int etb_store_reg(reg_t *reg) -{ - return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size)); -} - -static int etb_register_commands(struct command_context_s *cmd_ctx) -{ - command_t *etb_cmd; - - etb_cmd = register_command(cmd_ctx, NULL, "etb", NULL, COMMAND_ANY, "Embedded Trace Buffer"); - - register_command(cmd_ctx, etb_cmd, "config", handle_etb_config_command, COMMAND_CONFIG, NULL); - - return ERROR_OK; -} - -static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_etb_config_command) { target_t *target; - jtag_tap_t *tap; - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; + struct jtag_tap *tap; + struct arm *arm; if (argc != 2) { @@ -377,28 +364,29 @@ static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cm if (!target) { - LOG_ERROR("target '%s' not defined", args[0]); + LOG_ERROR("ETB: target '%s' not defined", args[0]); return ERROR_FAIL; } - if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) + arm = target_to_arm(target); + if (!is_arm(arm)) { - command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target"); + command_print(cmd_ctx, "ETB: '%s' isn't an ARM", args[0]); return ERROR_FAIL; } - tap = jtag_tap_by_string(args[1] ); + tap = jtag_tap_by_string(args[1]); if (tap == NULL) { - command_print(cmd_ctx, "Tap: %s does not exist", args[1] ); + command_print(cmd_ctx, "ETB: TAP %s does not exist", args[1]); return ERROR_FAIL; } - if (arm7_9->etm_ctx) + if (arm->etm) { etb_t *etb = malloc(sizeof(etb_t)); - arm7_9->etm_ctx->capture_driver_priv = etb; + arm->etm->capture_driver_priv = etb; etb->tap = tap; etb->cur_scan_chain = 0xffffffff; @@ -408,13 +396,25 @@ static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cm } else { - LOG_ERROR("target has no ETM defined, ETB left unconfigured"); + LOG_ERROR("ETM: target has no ETM defined, ETB left unconfigured"); return ERROR_FAIL; } return ERROR_OK; } +static int etb_register_commands(struct command_context_s *cmd_ctx) +{ + command_t *etb_cmd = register_command(cmd_ctx, NULL, "etb", + NULL, COMMAND_ANY, "Embedded Trace Buffer"); + + register_command(cmd_ctx, etb_cmd, "config", + handle_etb_config_command, COMMAND_CONFIG, + NULL); + + return ERROR_OK; +} + static int etb_init(etm_context_t *etm_ctx) { etb_t *etb = etm_ctx->capture_driver_priv; @@ -435,56 +435,53 @@ static int etb_init(etm_context_t *etm_ctx) static trace_status_t etb_status(etm_context_t *etm_ctx) { etb_t *etb = etm_ctx->capture_driver_priv; + reg_t *control = &etb->reg_cache->reg_list[ETB_CTRL]; + reg_t *status = &etb->reg_cache->reg_list[ETB_STATUS]; + trace_status_t retval = 0; + int etb_timeout = 100; etb->etm_ctx = etm_ctx; - /* if tracing is currently idle, return this information */ - if (etm_ctx->capture_status == TRACE_IDLE) - { - return etm_ctx->capture_status; - } - else if (etm_ctx->capture_status & TRACE_RUNNING) - { - reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS]; - int etb_timeout = 100; + /* read control and status registers */ + etb_read_reg(control); + etb_read_reg(status); + jtag_execute_queue(); - /* trace is running, check the ETB status flags */ - etb_get_reg(etb_status_reg); + /* See if it's (still) active */ + retval = buf_get_u32(control->value, 0, 1) ? TRACE_RUNNING : TRACE_IDLE; - /* check Full bit to identify an overflow */ - if (buf_get_u32(etb_status_reg->value, 0, 1) == 1) - etm_ctx->capture_status |= TRACE_OVERFLOWED; + /* check Full bit to identify wraparound/overflow */ + if (buf_get_u32(status->value, 0, 1) == 1) + retval |= TRACE_OVERFLOWED; - /* check Triggered bit to identify trigger condition */ - if (buf_get_u32(etb_status_reg->value, 1, 1) == 1) - etm_ctx->capture_status |= TRACE_TRIGGERED; + /* check Triggered bit to identify trigger condition */ + if (buf_get_u32(status->value, 1, 1) == 1) + retval |= TRACE_TRIGGERED; - /* check AcqComp to identify trace completion */ - if (buf_get_u32(etb_status_reg->value, 2, 1) == 1) - { - while (etb_timeout-- && (buf_get_u32(etb_status_reg->value, 3, 1) == 0)) - { - /* wait for data formatter idle */ - etb_get_reg(etb_status_reg); - } + /* check AcqComp to see if trigger counter dropped to zero */ + if (buf_get_u32(status->value, 2, 1) == 1) { + /* wait for DFEmpty */ + while (etb_timeout-- && buf_get_u32(status->value, 3, 1) == 0) + etb_get_reg(status); - if (etb_timeout == 0) - { - LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%" PRIx32 "", - buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size)); - } + if (etb_timeout == 0) + LOG_ERROR("ETB: DFEmpty won't go high, status 0x%02x", + (unsigned) buf_get_u32(status->value, 0, 4)); - if (!(etm_ctx->capture_status && TRACE_TRIGGERED)) - { - LOG_ERROR("trace completed, but no trigger condition detected"); - } + if (!(etm_ctx->capture_status & TRACE_TRIGGERED)) + LOG_WARNING("ETB: trace complete without triggering?"); - etm_ctx->capture_status &= ~TRACE_RUNNING; - etm_ctx->capture_status |= TRACE_COMPLETED; - } + retval |= TRACE_COMPLETED; } - return etm_ctx->capture_status; + /* NOTE: using a trigger is optional; and at least ETB11 has a mode + * where it can ignore the trigger counter. + */ + + /* update recorded state */ + etm_ctx->capture_status = retval; + + return retval; } static int etb_read_trace(etm_context_t *etm_ctx) @@ -653,8 +650,10 @@ static int etb_start_capture(etm_context_t *etm_ctx) etb_ctrl_value |= 0x2; } - if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) + if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) { + LOG_ERROR("ETB: can't run in multiplexed mode"); return ERROR_ETM_PORTMODE_NOT_SUPPORTED; + } trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;