X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fetm.c;h=48d2ebaf3a1150001faba2ec4e115d80eef868ec;hb=83655bf49bfa03b0c57c20123984cf09c4c09393;hp=ab368781eee1793c2095d2566efa5bbe107133fe;hpb=4d88c124b1262a738b4a9f107ef62404a45bf323;p=openocd.git diff --git a/src/target/etm.c b/src/target/etm.c index ab368781ee..48d2ebaf3a 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -21,26 +21,12 @@ #include "config.h" #endif -#include - #include "etm.h" #include "etb.h" - -#include "armv4_5.h" +#include "image.h" #include "arm7_9_common.h" #include "arm_disassembler.h" -#include "arm_simulator.h" - -#include "log.h" -#include "arm_jtag.h" -#include "types.h" -#include "binarybuffer.h" -#include "target.h" -#include "register.h" -#include "jtag.h" -#include "fileio.h" -#include /* ETM register access functionality * @@ -275,11 +261,12 @@ reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_co int etm_setup(target_t *target) { int retval; - u32 etm_ctrl_value; + uint32_t etm_ctrl_value; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; etm_context_t *etm_ctx = arm7_9->etm_ctx; reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL]; + /* initialize some ETM control register settings */ etm_get_reg(etm_ctrl_reg); etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size); @@ -295,10 +282,10 @@ int etm_setup(target_t *target) buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value); etm_store_reg(etm_ctrl_reg); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; - if ((retval=etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK) + if ((retval = etm_ctx->capture_driver->init(etm_ctx)) != ERROR_OK) { LOG_ERROR("ETM capture driver initialization failed"); return retval; @@ -309,6 +296,7 @@ int etm_setup(target_t *target) int etm_get_reg(reg_t *reg) { int retval; + if ((retval = etm_read_reg(reg)) != ERROR_OK) { LOG_ERROR("BUG: error scheduling etm register read"); @@ -324,56 +312,48 @@ int etm_get_reg(reg_t *reg) return ERROR_OK; } -int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) +int etm_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask) { etm_reg_t *etm_reg = reg->arch_info; - u8 reg_addr = etm_reg->addr & 0x7f; + uint8_t reg_addr = etm_reg->addr & 0x7f; scan_field_t fields[3]; LOG_DEBUG("%i", etm_reg->addr); - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(etm_reg->jtag_info, 0x6); arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL); fields[0].tap = etm_reg->jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = reg->value; - fields[0].in_value = NULL; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; + fields[0].check_value = NULL; + fields[0].check_mask = NULL; fields[1].tap = etm_reg->jtag_info->tap; fields[1].num_bits = 7; fields[1].out_value = malloc(1); buf_set_u32(fields[1].out_value, 0, 7, reg_addr); - fields[1].in_value = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; + fields[1].check_value = NULL; + fields[1].check_mask = NULL; fields[2].tap = etm_reg->jtag_info->tap; fields[2].num_bits = 1; fields[2].out_value = malloc(1); buf_set_u32(fields[2].out_value, 0, 1, 0); - fields[2].in_value = NULL; - fields[2].in_check_value = NULL; - fields[2].in_check_mask = NULL; - fields[2].in_handler = NULL; - fields[2].in_handler_priv = NULL; + fields[2].check_value = NULL; + fields[2].check_mask = NULL; - jtag_add_dr_scan(3, fields, TAP_INVALID); + jtag_add_dr_scan(3, fields, jtag_get_end_state()); fields[0].in_value = reg->value; - jtag_set_check_value(fields+0, check_value, check_mask, NULL); + fields[0].check_value = check_value; + fields[0].check_mask = check_mask; - jtag_add_dr_scan(3, fields, TAP_INVALID); + jtag_add_dr_scan_check(3, fields, jtag_get_end_state()); free(fields[1].out_value); free(fields[2].out_value); @@ -386,9 +366,10 @@ int etm_read_reg(reg_t *reg) return etm_read_reg_w_check(reg, NULL, NULL); } -int etm_set_reg(reg_t *reg, u32 value) +int etm_set_reg(reg_t *reg, uint32_t value) { int retval; + if ((retval = etm_write_reg(reg, value)) != ERROR_OK) { LOG_ERROR("BUG: error scheduling etm register write"); @@ -402,9 +383,10 @@ int etm_set_reg(reg_t *reg, u32 value) return ERROR_OK; } -int etm_set_reg_w_exec(reg_t *reg, u8 *buf) +int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf) { int retval; + etm_set_reg(reg, buf_get_u32(buf, 0, reg->size)); if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -415,56 +397,40 @@ int etm_set_reg_w_exec(reg_t *reg, u8 *buf) return ERROR_OK; } -int etm_write_reg(reg_t *reg, u32 value) +int etm_write_reg(reg_t *reg, uint32_t value) { etm_reg_t *etm_reg = reg->arch_info; - u8 reg_addr = etm_reg->addr & 0x7f; + uint8_t reg_addr = etm_reg->addr & 0x7f; scan_field_t fields[3]; - LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value); + LOG_DEBUG("%i: 0x%8.8" PRIx32 "", etm_reg->addr, value); - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(etm_reg->jtag_info, 0x6); arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL); fields[0].tap = etm_reg->jtag_info->tap; fields[0].num_bits = 32; - fields[0].out_value = malloc(4); + uint8_t tmp1[4]; + fields[0].out_value = tmp1; buf_set_u32(fields[0].out_value, 0, 32, value); - fields[0].in_value = NULL; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; fields[1].tap = etm_reg->jtag_info->tap; fields[1].num_bits = 7; - fields[1].out_value = malloc(1); + uint8_t tmp2; + fields[1].out_value = &tmp2; buf_set_u32(fields[1].out_value, 0, 7, reg_addr); - fields[1].in_value = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; fields[2].tap = etm_reg->jtag_info->tap; fields[2].num_bits = 1; - fields[2].out_value = malloc(1); + uint8_t tmp3; + fields[2].out_value = &tmp3; buf_set_u32(fields[2].out_value, 0, 1, 1); - fields[2].in_value = NULL; - fields[2].in_check_value = NULL; - fields[2].in_check_mask = NULL; - fields[2].in_handler = NULL; - fields[2].in_handler_priv = NULL; - - jtag_add_dr_scan(3, fields, TAP_INVALID); - free(fields[0].out_value); - free(fields[1].out_value); - free(fields[2].out_value); + jtag_add_dr_scan(3, fields, jtag_get_end_state()); return ERROR_OK; } @@ -508,8 +474,8 @@ static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instructi { int i; int section = -1; - u32 size_read; - u32 opcode; + uint32_t size_read; + uint32_t opcode; int retval; if (!ctx->image) @@ -534,7 +500,7 @@ static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instructi if (ctx->core_state == ARMV4_5_STATE_ARM) { - u8 buf[4]; + uint8_t buf[4]; if ((retval = image_read_section(ctx->image, section, ctx->current_pc - ctx->image->sections[section].base_address, 4, buf, &size_read)) != ERROR_OK) @@ -547,7 +513,7 @@ static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instructi } else if (ctx->core_state == ARMV4_5_STATE_THUMB) { - u8 buf[2]; + uint8_t buf[2]; if ((retval = image_read_section(ctx->image, section, ctx->current_pc - ctx->image->sections[section].base_address, 2, buf, &size_read)) != ERROR_OK) @@ -572,7 +538,7 @@ static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instructi return ERROR_OK; } -static int etmv1_next_packet(etm_context_t *ctx, u8 *packet, int apo) +static int etmv1_next_packet(etm_context_t *ctx, uint8_t *packet, int apo) { while (ctx->data_index < ctx->trace_depth) { @@ -640,10 +606,10 @@ static int etmv1_next_packet(etm_context_t *ctx, u8 *packet, int apo) static int etmv1_branch_address(etm_context_t *ctx) { int retval; - u8 packet; + uint8_t packet; int shift = 0; int apo; - u32 i; + uint32_t i; /* quit analysis if less than two cycles are left in the trace * because we can't extract the APO */ @@ -723,10 +689,10 @@ static int etmv1_branch_address(etm_context_t *ctx) return 0; } -static int etmv1_data(etm_context_t *ctx, int size, u32 *data) +static int etmv1_data(etm_context_t *ctx, int size, uint32_t *data) { int j; - u8 buf[4]; + uint8_t buf[4]; int retval; for (j = 0; j < size; j++) @@ -772,13 +738,13 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd while (ctx->pipe_index < ctx->trace_depth) { - u8 pipestat = ctx->trace_data[ctx->pipe_index].pipestat; - u32 next_pc = ctx->current_pc; - u32 old_data_index = ctx->data_index; - u32 old_data_half = ctx->data_half; - u32 old_index = ctx->pipe_index; - u32 last_instruction = ctx->last_instruction; - u32 cycles = 0; + uint8_t pipestat = ctx->trace_data[ctx->pipe_index].pipestat; + uint32_t next_pc = ctx->current_pc; + uint32_t old_data_index = ctx->data_index; + uint32_t old_data_half = ctx->data_half; + uint32_t old_index = ctx->pipe_index; + uint32_t last_instruction = ctx->last_instruction; + uint32_t cycles = 0; int current_pc_ok = ctx->pc_ok; if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE) @@ -835,19 +801,19 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd next_pc = ctx->last_branch; break; case 0x1: /* tracing enabled */ - command_print(cmd_ctx, "--- tracing enabled at 0x%8.8x ---", ctx->last_branch); + command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch); ctx->current_pc = ctx->last_branch; ctx->pipe_index++; continue; break; case 0x2: /* trace restarted after FIFO overflow */ - command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8x ---", ctx->last_branch); + command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch); ctx->current_pc = ctx->last_branch; ctx->pipe_index++; continue; break; case 0x3: /* exit from debug state */ - command_print(cmd_ctx, "--- exit from debug state at 0x%8.8x ---", ctx->last_branch); + command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch); ctx->current_pc = ctx->last_branch; ctx->pipe_index++; continue; @@ -859,14 +825,14 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd */ if (!current_pc_ok) { - command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8x ---", next_pc); + command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc); ctx->current_pc = next_pc; ctx->pipe_index++; continue; } break; default: /* reserved */ - LOG_ERROR("BUG: branch reason code 0x%x is reserved", ctx->last_branch_reason); + LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason); exit(-1); break; } @@ -888,7 +854,7 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd } else { - command_print(cmd_ctx, "exception vector 0x%2.2x", ctx->last_branch); + command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch); ctx->current_pc = ctx->last_branch; ctx->pipe_index++; continue; @@ -922,8 +888,8 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd if ((pipestat == STAT_ID) || (pipestat == STAT_BD)) { - u32 new_data_index = ctx->data_index; - u32 new_data_half = ctx->data_half; + uint32_t new_data_index = ctx->data_index; + uint32_t new_data_half = ctx->data_half; /* in case of a branch with data, the branch target address was consumed before * we temporarily go back to the saved data index */ @@ -935,7 +901,7 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd if (ctx->tracemode & ETMV1_TRACE_ADDR) { - u8 packet; + uint8_t packet; int shift = 0; do { @@ -951,7 +917,7 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd if (ctx->ptr_ok) { - command_print(cmd_ctx, "address: 0x%8.8x", ctx->last_ptr); + command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr); } } @@ -964,19 +930,19 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd { if (instruction.info.load_store_multiple.register_list & (1 << i)) { - u32 data; + uint32_t data; if (etmv1_data(ctx, 4, &data) != 0) return ERROR_ETM_ANALYSIS_FAILED; - command_print(cmd_ctx, "data: 0x%8.8x", data); + command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data); } } } else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_STRH)) { - u32 data; + uint32_t data; if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0) return ERROR_ETM_ANALYSIS_FAILED; - command_print(cmd_ctx, "data: 0x%8.8x", data); + command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data); } } @@ -993,7 +959,7 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd { if (((instruction.type == ARM_B) || (instruction.type == ARM_BL) || - (instruction.type == ARM_BLX)) && + (instruction.type == ARM_BLX)) && (instruction.info.b_bl_bx_blx.target_address != 0xffffffff)) { next_pc = instruction.info.b_bl_bx_blx.target_address; @@ -1018,7 +984,7 @@ static int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd if (ctx->tracemode & ETMV1_CYCLE_ACCURATE) { snprintf(cycles_text, 32, " (%i %s)", - cycles, + (int)cycles, (cycles == 1) ? "cycle" : "cycles"); } @@ -1141,7 +1107,7 @@ static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char } else if (argc != 0) { - command_print(cmd_ctx, "usage: configure trace mode "); + command_print(cmd_ctx, "usage: configure trace mode "); return ERROR_OK; } @@ -1239,11 +1205,10 @@ static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cm return ERROR_COMMAND_SYNTAX_ERROR; } - target = get_target_by_num(strtoul(args[0], NULL, 0)); - + target = get_target(args[0]); if (!target) { - LOG_ERROR("target number '%s' not defined", args[0]); + LOG_ERROR("target '%s' not defined", args[0]); return ERROR_FAIL; } @@ -1301,12 +1266,12 @@ static int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cm return ERROR_FAIL; } - for (i=0; etm_capture_drivers[i]; i++) + for (i = 0; etm_capture_drivers[i]; i++) { if (strcmp(args[4], etm_capture_drivers[i]->name) == 0) { int retval; - if ((retval=etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK) + if ((retval = etm_capture_drivers[i]->register_commands(cmd_ctx)) != ERROR_OK) { free(etm_ctx); return retval; @@ -1378,17 +1343,17 @@ int handle_etm_info_command(struct command_context_s *cmd_ctx, char *cmd, char * etm_sys_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_SYS_CONFIG]; etm_get_reg(etm_config_reg); - command_print(cmd_ctx, "pairs of address comparators: %i", buf_get_u32(etm_config_reg->value, 0, 4)); - command_print(cmd_ctx, "pairs of data comparators: %i", buf_get_u32(etm_config_reg->value, 4, 4)); - command_print(cmd_ctx, "memory map decoders: %i", buf_get_u32(etm_config_reg->value, 8, 5)); - command_print(cmd_ctx, "number of counters: %i", buf_get_u32(etm_config_reg->value, 13, 3)); + command_print(cmd_ctx, "pairs of address comparators: %i", (int)buf_get_u32(etm_config_reg->value, 0, 4)); + command_print(cmd_ctx, "pairs of data comparators: %i", (int)buf_get_u32(etm_config_reg->value, 4, 4)); + command_print(cmd_ctx, "memory map decoders: %i", (int)buf_get_u32(etm_config_reg->value, 8, 5)); + command_print(cmd_ctx, "number of counters: %i", (int)buf_get_u32(etm_config_reg->value, 13, 3)); command_print(cmd_ctx, "sequencer %spresent", (buf_get_u32(etm_config_reg->value, 16, 1) == 1) ? "" : "not "); - command_print(cmd_ctx, "number of ext. inputs: %i", buf_get_u32(etm_config_reg->value, 17, 3)); - command_print(cmd_ctx, "number of ext. outputs: %i", buf_get_u32(etm_config_reg->value, 20, 3)); + command_print(cmd_ctx, "number of ext. inputs: %i", (int)buf_get_u32(etm_config_reg->value, 17, 3)); + command_print(cmd_ctx, "number of ext. outputs: %i",(int) buf_get_u32(etm_config_reg->value, 20, 3)); command_print(cmd_ctx, "FIFO full %spresent", (buf_get_u32(etm_config_reg->value, 23, 1) == 1) ? "" : "not "); - command_print(cmd_ctx, "protocol version: %i", buf_get_u32(etm_config_reg->value, 28, 3)); + command_print(cmd_ctx, "protocol version: %i", (int)buf_get_u32(etm_config_reg->value, 28, 3)); etm_get_reg(etm_sys_config_reg); @@ -1466,7 +1431,7 @@ static int handle_etm_status_command(struct command_context_s *cmd_ctx, char *cm if (arm7_9->etm_ctx->trace_depth > 0) { - command_print(cmd_ctx, "%i frames of trace data read", arm7_9->etm_ctx->trace_depth); + command_print(cmd_ctx, "%i frames of trace data read", (int)(arm7_9->etm_ctx->trace_depth)); } } @@ -1539,7 +1504,7 @@ static int handle_etm_dump_command(struct command_context_s *cmd_ctx, char *cmd, armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; etm_context_t *etm_ctx; - u32 i; + uint32_t i; if (argc != 1) { @@ -1607,7 +1572,7 @@ static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; etm_context_t *etm_ctx; - u32 i; + uint32_t i; if (argc != 1) { @@ -1653,13 +1618,15 @@ static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, etm_ctx->trace_data = NULL; } - fileio_read_u32(&file, &etm_ctx->capture_status); - fileio_read_u32(&file, &etm_ctx->portmode); - fileio_read_u32(&file, &etm_ctx->tracemode); - fileio_read_u32(&file, &etm_ctx->trace_depth); - + { + uint32_t tmp; + fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp; + fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp; + fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp; + fileio_read_u32(&file, &etm_ctx->trace_depth); + } etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth); - if(etm_ctx->trace_data == NULL) + if (etm_ctx->trace_data == NULL) { command_print(cmd_ctx, "not enough memory to perform operation"); fileio_close(&file); @@ -1668,7 +1635,7 @@ static int handle_etm_load_command(struct command_context_s *cmd_ctx, char *cmd, for (i = 0; i < etm_ctx->trace_depth; i++) { - u32 pipestat, packet, flags; + uint32_t pipestat, packet, flags; fileio_read_u32(&file, &pipestat); fileio_read_u32(&file, &packet); fileio_read_u32(&file, &flags); @@ -1705,11 +1672,11 @@ static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, if (argc > 0) { - u32 new_value = strtoul(args[0], NULL, 0); + uint32_t new_value = strtoul(args[0], NULL, 0); if ((new_value < 2) || (new_value > 100)) { - command_print(cmd_ctx, "valid settings are 2% to 100%"); + command_print(cmd_ctx, "valid settings are 2%% to 100%%"); } else { @@ -1717,7 +1684,7 @@ static int handle_etm_trigger_percent_command(struct command_context_s *cmd_ctx, } } - command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", etm_ctx->trigger_percent); + command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent))); return ERROR_OK; } @@ -1827,7 +1794,7 @@ static int handle_etm_analyze_command(struct command_context_s *cmd_ctx, char *c if ((retval = etmv1_analyze_trace(etm_ctx, cmd_ctx)) != ERROR_OK) { - switch(retval) + switch (retval) { case ERROR_ETM_ANALYSIS_FAILED: command_print(cmd_ctx, "further analysis failed (corrupted trace data or just end of data"); @@ -1850,7 +1817,8 @@ int etm_register_commands(struct command_context_s *cmd_ctx) { etm_cmd = register_command(cmd_ctx, NULL, "etm", NULL, COMMAND_ANY, "Embedded Trace Macrocell"); - register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command, COMMAND_CONFIG, "etm config "); + register_command(cmd_ctx, etm_cmd, "config", handle_etm_config_command, + COMMAND_CONFIG, "etm config "); return ERROR_OK; } @@ -1858,12 +1826,13 @@ int etm_register_commands(struct command_context_s *cmd_ctx) int etm_register_user_commands(struct command_context_s *cmd_ctx) { register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command, - COMMAND_EXEC, "configure trace mode " + " "); register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command, COMMAND_EXEC, "display info about the current target's ETM"); - register_command(cmd_ctx, etm_cmd, "trigger_percent ", handle_etm_trigger_percent_command, + register_command(cmd_ctx, etm_cmd, "trigger_percent", handle_etm_trigger_percent_command, COMMAND_EXEC, "amount () of trace buffer to be filled after the trigger occured"); register_command(cmd_ctx, etm_cmd, "status", handle_etm_status_command, COMMAND_EXEC, "display current target's ETM status");