X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fevent%2Fstr912_reset.script;h=c3d6810447aca87cbfe8ad21cc4581bcbec8ceb1;hb=23939e4fc3400aa6f781ac364d9fd8c2cf66449a;hp=8178c82c702f987d4e2834858951a3a02913ac6e;hpb=349f62f74fdc1278efd00a0e6301e1a0199cc128;p=openocd.git

diff --git a/src/target/event/str912_reset.script b/src/target/event/str912_reset.script
index 8178c82c70..c3d6810447 100644
--- a/src/target/event/str912_reset.script
+++ b/src/target/event/str912_reset.script
@@ -1,21 +1,22 @@
-mww 0xFFFFFD44, 0x00008000 #Disable watchdog
-mww 0xFFFFFC20, 0x00000601 #Enable Main oscillator
-sleep 20
-mww 0xFFFFFC30, 0x00000001 #Switch master clock to CPU clock, write 1 to PMC_MCKR
-sleep 20
-
-
-# -- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,
-#    when the bank 0 is the boot bank, then enable the Bank 1. */
-
-mww 0x54000000, 0x4 #BOOT BANK Size = (2^4) * 32 = 512KB
-mww 0x54000004, 0x2 #NON BOOT BANK Size = (2^2) * 8 = 32KB
-mww 0x5400000C, 0x0 #BOOT BANK Address = 0x0
-mww 0x54000010, 0x20000 #NON BOOT BANK Address = 0x80000
-mww 0x54000018, 0x18 #Enable CS on both banks
-
-# -- Enable 96K RAM */
-mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled
-arm966e cp15 15, 0x60000 #Set bits 17-18 (DTCM/ITCM order bits) of the Core Configuration Control Register
-
-flash protect 0 0 7 off
+mww 0xFFFFFD44, 0x00008000 #Disable watchdog
+mww 0xFFFFFC20, 0x00000601 #Enable Main oscillator
+sleep 20
+mww 0xFFFFFC30, 0x00000001 #Switch master clock to CPU clock, write 1 to PMC_MCKR
+sleep 20
+
+
+# -- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,
+#    when the bank 0 is the boot bank, then enable the Bank 1. */
+
+mww 0x54000000, 0x4 #BOOT BANK Size = (2^4) * 32 = 512KB
+mww 0x54000004, 0x2 #NON BOOT BANK Size = (2^2) * 8 = 32KB
+mww 0x5400000C, 0x0 #BOOT BANK Address = 0x0
+mww 0x54000010, 0x20000 #NON BOOT BANK Address = 0x80000
+mww 0x54000018, 0x18 #Enable CS on both banks
+
+# -- Enable 96K RAM */
+mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled
+arm966e cp15 15, 0x60000 #Set bits 17-18 (DTCM/ITCM order bits) of the Core Configuration Control Register
+
+str9x flash_config 0 4 2 0 0x80000
+flash protect 0 0 7 off