X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fferoceon.c;h=2152a260135f59b0f6ff7d3f30ba028e40e46529;hb=4cc359794420dbe0aedba38bde0ee4d871cdb354;hp=c912137627f6b32ce883c0b3ba8a04351adbab79;hpb=a4a2808c2a849eddd5d7d454c048ffdfd89ca9c6;p=openocd.git

diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index c912137627..2152a26013 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -59,7 +59,7 @@
 #include "arm_opcodes.h"
 
 
-int feroceon_assert_reset(struct target *target)
+static int feroceon_assert_reset(struct target *target)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -72,46 +72,48 @@ int feroceon_assert_reset(struct target *target)
 	return arm7_9_assert_reset(target);
 }
 
-int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
+static int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
 {
 	struct scan_field fields[3];
 	uint8_t out_buf[4];
 	uint8_t instr_buf[4];
 	uint8_t sysspeed_buf = 0x0;
+	int retval;
 
 	/* prepare buffer */
 	buf_set_u32(out_buf, 0, 32, 0);
 
 	buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
 
-	jtag_set_end_state(TAP_DRPAUSE);
-	arm_jtag_scann(jtag_info, 0x1);
+	retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
+	if (retval != ERROR_OK)
+		return retval;
 
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+	if (retval != ERROR_OK)
+		return retval;
 
-	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = out_buf;
 	fields[0].in_value = NULL;
 
-	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 3;
 	fields[1].out_value = &sysspeed_buf;
 	fields[1].in_value = NULL;
 
-	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 32;
 	fields[2].out_value = instr_buf;
 	fields[2].in_value = NULL;
 
-	jtag_add_dr_scan(3, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE);
 
-	/* no jtag_add_runtest(0, jtag_get_end_state()) here */
+	/* no jtag_add_runtest(0, TAP_DRPAUSE) here */
 
 	return ERROR_OK;
 }
 
-void feroceon_change_to_arm(struct target *target, uint32_t *r0, uint32_t *pc)
+static void feroceon_change_to_arm(struct target *target, uint32_t *r0,
+		uint32_t *pc)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -157,7 +159,8 @@ void feroceon_change_to_arm(struct target *target, uint32_t *r0, uint32_t *pc)
 	*pc -= (12 + 4);
 }
 
-void feroceon_read_core_regs(struct target *target, uint32_t mask, uint32_t* core_regs[16])
+static void feroceon_read_core_regs(struct target *target,
+		uint32_t mask, uint32_t* core_regs[16])
 {
 	int i;
 	struct arm *armv4_5 = target->arch_info;
@@ -176,7 +179,8 @@ void feroceon_read_core_regs(struct target *target, uint32_t mask, uint32_t* cor
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_read_core_regs_target_buffer(struct target *target, uint32_t mask, void* buffer, int size)
+static void feroceon_read_core_regs_target_buffer(struct target *target,
+		uint32_t mask, void* buffer, int size)
 {
 	int i;
 	struct arm *armv4_5 = target->arch_info;
@@ -213,7 +217,7 @@ void feroceon_read_core_regs_target_buffer(struct target *target, uint32_t mask,
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
+static void feroceon_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -236,7 +240,7 @@ void feroceon_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
+static void feroceon_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -277,7 +281,8 @@ void feroceon_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_write_xpsr_im8(struct target *target, uint8_t xpsr_im, int rot, int spsr)
+static void feroceon_write_xpsr_im8(struct target *target,
+		uint8_t xpsr_im, int rot, int spsr)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -294,7 +299,8 @@ void feroceon_write_xpsr_im8(struct target *target, uint8_t xpsr_im, int rot, in
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_write_core_regs(struct target *target, uint32_t mask, uint32_t core_regs[16])
+static void feroceon_write_core_regs(struct target *target,
+		uint32_t mask, uint32_t core_regs[16])
 {
 	int i;
 	struct arm *armv4_5 = target->arch_info;
@@ -314,7 +320,7 @@ void feroceon_write_core_regs(struct target *target, uint32_t mask, uint32_t cor
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 }
 
-void feroceon_branch_resume(struct target *target)
+static void feroceon_branch_resume(struct target *target)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -329,7 +335,7 @@ void feroceon_branch_resume(struct target *target)
 	arm7_9->need_bypass_before_restart = 1;
 }
 
-void feroceon_branch_resume_thumb(struct target *target)
+static void feroceon_branch_resume_thumb(struct target *target)
 {
 	LOG_DEBUG("-");
 
@@ -337,7 +343,7 @@ void feroceon_branch_resume_thumb(struct target *target)
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
 	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 	uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
-	uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+	uint32_t pc = buf_get_u32(armv4_5->pc->value, 0, 32);
 
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -364,7 +370,8 @@ void feroceon_branch_resume_thumb(struct target *target)
 	arm7_9->need_bypass_before_restart = 1;
 }
 
-int feroceon_read_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+static int feroceon_read_cp15(struct target *target, uint32_t op1,
+		uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -386,7 +393,8 @@ int feroceon_read_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32
 	return jtag_execute_queue();
 }
 
-int feroceon_write_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+static int feroceon_write_cp15(struct target *target, uint32_t op1,
+		uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -405,7 +413,7 @@ int feroceon_write_cp15(struct target *target, uint32_t op1, uint32_t op2, uint3
 	return arm7_9_execute_sys_speed(target);
 }
 
-void feroceon_set_dbgrq(struct target *target)
+static void feroceon_set_dbgrq(struct target *target)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -415,7 +423,7 @@ void feroceon_set_dbgrq(struct target *target)
 	embeddedice_store_reg(dbg_ctrl);
 }
 
-void feroceon_enable_single_step(struct target *target, uint32_t next_pc)
+static void feroceon_enable_single_step(struct target *target, uint32_t next_pc)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -428,7 +436,7 @@ void feroceon_enable_single_step(struct target *target, uint32_t next_pc)
 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
 }
 
-void feroceon_disable_single_step(struct target *target)
+static void feroceon_disable_single_step(struct target *target)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -440,7 +448,7 @@ void feroceon_disable_single_step(struct target *target)
 	embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
 }
 
-int feroceon_examine_debug_reason(struct target *target)
+static int feroceon_examine_debug_reason(struct target *target)
 {
 	/* the MOE is not implemented */
 	if (target->debug_reason != DBG_REASON_SINGLESTEP)
@@ -451,7 +459,8 @@ int feroceon_examine_debug_reason(struct target *target)
 	return ERROR_OK;
 }
 
-int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
+static int feroceon_bulk_write_memory(struct target *target,
+		uint32_t address, uint32_t count, uint8_t *buffer)
 {
 	int retval;
 	struct arm *armv4_5 = target->arch_info;
@@ -519,7 +528,7 @@ int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t
 	/* backup clobbered processor state */
 	for (i = 0; i <= 5; i++)
 		save[i] = buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32);
-	save[i] = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+	save[i] = buf_get_u32(armv4_5->pc->value, 0, 32);
 
 	/* set up target address in r0 */
 	buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
@@ -572,21 +581,22 @@ int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t
 		armv4_5->core_cache->reg_list[i].valid = 1;
 		armv4_5->core_cache->reg_list[i].dirty = 1;
 	}
-	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, save[i]);
-	armv4_5->core_cache->reg_list[15].valid = 1;
-	armv4_5->core_cache->reg_list[15].dirty = 1;
+	buf_set_u32(armv4_5->pc->value, 0, 32, save[i]);
+	armv4_5->pc->valid = 1;
+	armv4_5->pc->dirty = 1;
 	armv4_5->core_state = core_state;
 
 	return retval;
 }
 
-int feroceon_init_target(struct command_context *cmd_ctx, struct target *target)
+static int feroceon_init_target(struct command_context *cmd_ctx,
+		struct target *target)
 {
 	arm9tdmi_init_target(cmd_ctx, target);
 	return ERROR_OK;
 }
 
-void feroceon_common_setup(struct target *target)
+static void feroceon_common_setup(struct target *target)
 {
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
@@ -619,7 +629,7 @@ void feroceon_common_setup(struct target *target)
 	arm7_9->wp1_used_default = -1;
 }
 
-int feroceon_target_create(struct target *target, Jim_Interp *interp)
+static int feroceon_target_create(struct target *target, Jim_Interp *interp)
 {
 	struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common));
 
@@ -633,7 +643,7 @@ int feroceon_target_create(struct target *target, Jim_Interp *interp)
 	return ERROR_OK;
 }
 
-int dragonite_target_create(struct target *target, Jim_Interp *interp)
+static int dragonite_target_create(struct target *target, Jim_Interp *interp)
 {
 	struct arm966e_common *arm966e = calloc(1,sizeof(struct arm966e_common));
 
@@ -643,7 +653,7 @@ int dragonite_target_create(struct target *target, Jim_Interp *interp)
 	return ERROR_OK;
 }
 
-int feroceon_examine(struct target *target)
+static int feroceon_examine(struct target *target)
 {
 	struct arm *armv4_5;
 	struct arm7_9_common *arm7_9;
@@ -694,7 +704,7 @@ struct target_type feroceon_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm926ejs_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm926ejs_write_memory,
@@ -721,7 +731,7 @@ struct target_type dragonite_target =
 	.name = "dragonite",
 
 	.poll = arm7_9_poll,
-	.arch_state = armv4_5_arch_state,
+	.arch_state = arm_arch_state,
 
 	.target_request_data = arm7_9_target_request_data,
 
@@ -733,7 +743,7 @@ struct target_type dragonite_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm7_9_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm7_9_write_memory,