X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fmips32_dmaacc.c;h=9a38084106ed1a53b5e8c4ad2940e67a0cd8c975;hb=ebbc762182c943d5967ea106933181a2fb726b1b;hp=9727f4e8a44400c6e9b1f82fd6c8d72f65e133ef;hpb=de39cb772496a97f103583a9c23403269df8f0aa;p=openocd.git diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c index 9727f4e8a4..9a38084106 100644 --- a/src/target/mips32_dmaacc.c +++ b/src/target/mips32_dmaacc.c @@ -61,7 +61,7 @@ begin_ejtag_dma_read: do { ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); /* Read Data */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); @@ -107,7 +107,7 @@ begin_ejtag_dma_read_h: do { ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); /* Read Data */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); @@ -159,7 +159,7 @@ begin_ejtag_dma_read_b: do { ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); /* Read Data */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); @@ -191,7 +191,7 @@ begin_ejtag_dma_read_b: case 2: *data = (v >> 16) & 0xff; break; - case 3: + case 3: *data = (v >> 24) & 0xff; break; } @@ -226,7 +226,7 @@ begin_ejtag_dma_write: do { ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); /* Clear DMA & Check DERR */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); @@ -277,7 +277,7 @@ begin_ejtag_dma_write_h: do { ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); /* Clear DMA & Check DERR */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); @@ -329,7 +329,7 @@ begin_ejtag_dma_write_b: do { ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); + } while (ejtag_ctrl & EJTAG_CTRL_DSTRT); /* Clear DMA & Check DERR */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); @@ -369,8 +369,8 @@ int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, uint32_t addr, int count, int i; int retval; - for (i=0; i