X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fmips32_pracc.c;h=6b43479fccc601694b1c26afef71b7991498eacb;hb=e6d979eefcc99aeb3f95fab67598af461ef234c1;hp=52d31bdf76c8de742f619f88e9b9e419f4f24353;hpb=c68c2751f309103cc7116464e6c3242d54c1007b;p=openocd.git diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c index 52d31bdf76..6b43479fcc 100644 --- a/src/target/mips32_pracc.c +++ b/src/target/mips32_pracc.c @@ -6,6 +6,9 @@ * * * Copyright (C) 2009 by David N. Claffey * * * + * Copyright (C) 2011 by Drasko DRASKOVIC * + * drasko.draskovic@gmail.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -74,6 +77,8 @@ Nico Coesel #include "config.h" #endif +#include + #include "mips32.h" #include "mips32_pracc.h" @@ -90,19 +95,54 @@ struct mips32_pracc_context struct mips_ejtag *ejtag_info; }; +static int mips32_pracc_read_mem8(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, uint8_t *buf); +static int mips32_pracc_read_mem16(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, uint16_t *buf); +static int mips32_pracc_read_mem32(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, uint32_t *buf); +static int mips32_pracc_read_u32(struct mips_ejtag *ejtag_info, + uint32_t addr, uint32_t *buf); + +static int mips32_pracc_write_mem8(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, uint8_t *buf); +static int mips32_pracc_write_mem16(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, uint16_t *buf); +static int mips32_pracc_write_mem32(struct mips_ejtag *ejtag_info, + uint32_t addr, int count, uint32_t *buf); +static int mips32_pracc_write_u32(struct mips_ejtag *ejtag_info, + uint32_t addr, uint32_t *buf); + +static int mips32_pracc_sync_cache(struct mips_ejtag *ejtag_info, + uint32_t start_addr, uint32_t end_addr); +static int mips32_pracc_clean_invalidate_cache(struct mips_ejtag *ejtag_info, + uint32_t start_addr, uint32_t end_addr); + static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl) { uint32_t ejtag_ctrl; + long long then = timeval_ms(); + int timeout; + int retval; + + /* wait for the PrAcc to become "1" */ + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); + ejtag_ctrl = ejtag_info->ejtag_ctrl; while (1) { - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); - ejtag_ctrl = ejtag_info->ejtag_ctrl; - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + if (retval != ERROR_OK) + return retval; + if (ejtag_ctrl & EJTAG_CTRL_PRACC) break; - LOG_DEBUG("DEBUGMODULE: No memory access in progress!\n"); - return ERROR_JTAG_DEVICE_ERROR; + + if ( (timeout = timeval_ms()-then) > 1000 ) + { + LOG_DEBUG("DEBUGMODULE: No memory access in progress!"); + return ERROR_JTAG_DEVICE_ERROR; + } } *ctrl = ejtag_ctrl; @@ -149,18 +189,15 @@ static int mips32_pracc_exec_read(struct mips32_pracc_context *ctx, uint32_t add } /* Send the data out */ - mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL); - mips_ejtag_drscan_32(ctx->ejtag_info, &data); + mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA); + mips_ejtag_drscan_32_out(ctx->ejtag_info, data); /* Clear the access pending bit (let the processor eat!) */ ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; - mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL); - mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl); - - jtag_add_clocks(5); - jtag_execute_queue(); + mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL); + mips_ejtag_drscan_32_out(ctx->ejtag_info, ejtag_ctrl); - return ERROR_OK; + return jtag_execute_queue(); } static int mips32_pracc_exec_write(struct mips32_pracc_context *ctx, uint32_t address) @@ -168,17 +205,21 @@ static int mips32_pracc_exec_write(struct mips32_pracc_context *ctx, uint32_t ad uint32_t ejtag_ctrl,data; int offset; struct mips_ejtag *ejtag_info = ctx->ejtag_info; + int retval; - mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL); - mips_ejtag_drscan_32(ctx->ejtag_info, &data); + mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA); + retval = mips_ejtag_drscan_32(ctx->ejtag_info, &data); + if (retval != ERROR_OK) + return retval; /* Clear access pending bit */ ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; - mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL); - mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl); + mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL); + mips_ejtag_drscan_32_out(ctx->ejtag_info, ejtag_ctrl); - jtag_add_clocks(5); - jtag_execute_queue(); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; if ((address >= MIPS32_PRACC_PARAM_IN) && (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4)) @@ -206,7 +247,8 @@ static int mips32_pracc_exec_write(struct mips32_pracc_context *ctx, uint32_t ad return ERROR_OK; } -int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_t *code, int num_param_in, uint32_t *param_in, int num_param_out, uint32_t *param_out, int cycle) +int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_t *code, + int num_param_in, uint32_t *param_in, int num_param_out, uint32_t *param_out, int cycle) { uint32_t ejtag_ctrl; uint32_t address, data; @@ -229,8 +271,10 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_ return retval; address = data = 0; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); - mips_ejtag_drscan_32(ejtag_info, &address); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); + retval = mips_ejtag_drscan_32(ejtag_info, &address); + if (retval != ERROR_OK) + return retval; /* Check for read or write */ if (ejtag_ctrl & EJTAG_CTRL_PRNW) @@ -283,7 +327,7 @@ int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size return ERROR_OK; } -int mips32_pracc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf) +static int mips32_pracc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf) { static const uint32_t code[] = { /* start: */ @@ -353,7 +397,7 @@ int mips32_pracc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int co return retval; } -int mips32_pracc_read_u32(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *buf) +static int mips32_pracc_read_u32(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *buf) { static const uint32_t code[] = { /* start: */ @@ -386,7 +430,7 @@ int mips32_pracc_read_u32(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t return retval; } -int mips32_pracc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf) +static int mips32_pracc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf) { static const uint32_t code[] = { /* start: */ @@ -429,13 +473,10 @@ int mips32_pracc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int co uint32_t *param_out = malloc(count * sizeof(uint32_t)); int i; -// int retval; + int retval = ERROR_OK; int blocksize; - int bytesread; uint32_t param_in[2]; - bytesread = 0; - //while (count > 0) { blocksize = count; @@ -445,12 +486,11 @@ int mips32_pracc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int co param_in[0] = addr; param_in[1] = blocksize; - mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \ + retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, ARRAY_SIZE(param_in), param_in, count, param_out, 1); // count -= blocksize; // addr += blocksize; -// bytesread += blocksize; } for (i = 0; i < count; i++) @@ -460,10 +500,10 @@ int mips32_pracc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int co free(param_out); - return ERROR_OK; + return retval; } -int mips32_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf) +static int mips32_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf) { static const uint32_t code[] = { /* start: */ @@ -506,13 +546,10 @@ int mips32_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int cou uint32_t *param_out = malloc(count * sizeof(uint32_t)); int i; -// int retval; + int retval = ERROR_OK; int blocksize; - int bytesread; uint32_t param_in[2]; - bytesread = 0; - // while (count > 0) { blocksize = count; @@ -522,12 +559,11 @@ int mips32_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int cou param_in[0] = addr; param_in[1] = blocksize; - mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \ + retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, ARRAY_SIZE(param_in), param_in, count, param_out, 1); // count -= blocksize; // addr += blocksize; -// bytesread += blocksize; } for (i = 0; i < count; i++) @@ -537,28 +573,344 @@ int mips32_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int cou free(param_out); - return ERROR_OK; + return retval; +} + +int mips32_cp0_read(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel) +{ + /** + * Do not make this code static, but regenerate it every time, + * as 5th element has to be changed to add parameters + */ + uint32_t code[] = { + /* start: */ + MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(8,0,15), /* sw $8,($15) */ + MIPS32_SW(9,0,15), /* sw $9,($15) */ + + /* 5 */ MIPS32_MFC0(8,0,0), /* move COP0 [cp0_reg select] to $8 */ + + MIPS32_LUI(9,UPPER16(MIPS32_PRACC_PARAM_OUT)), /* $11 = MIPS32_PRACC_PARAM_OUT */ + MIPS32_ORI(9,9,LOWER16(MIPS32_PRACC_PARAM_OUT)), + MIPS32_SW(8,0,9), /* sw $8,0($9) */ + + MIPS32_LW(9,0,15), /* lw $9,($15) */ + MIPS32_LW(8,0,15), /* lw $8,($15) */ + MIPS32_B(NEG16(12)), /* b start */ + MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + }; + + /** + * Note that our input parametes cp0_reg and cp0_sel + * are numbers (not gprs) which make part of mfc0 instruction opcode. + * + * These are not fix, but can be different for each mips32_cp0_read() function call, + * and that is why we must insert them directly into opcode, + * i.e. we can not pass it on EJTAG microprogram stack (via param_in), + * and put them into the gprs later from MIPS32_PRACC_STACK + * because mfc0 do not use gpr as a parameter for the cp0_reg and select part, + * but plain (immediate) number. + * + * MIPS32_MTC0 is implemented via MIPS32_R_INST macro. + * In order to insert our parameters, we must change rd and funct fields. + */ + code[5] |= (cp0_reg << 11) | cp0_sel; /* change rd and funct of MIPS32_R_INST macro */ + + /* TODO remove array */ + uint32_t *param_out = val; + int retval; + + retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 0, NULL, 1, param_out, 1); + + return retval; +} + +int mips32_cp0_write(struct mips_ejtag *ejtag_info, + uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel) +{ + uint32_t code[] = { + /* start: */ + MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(8,0,15), /* sw $8,($15) */ + MIPS32_SW(9,0,15), /* sw $9,($15) */ + + MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ + MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), + MIPS32_LW(9,0,8), /* Load write val to $9 */ + + /* 8 */ MIPS32_MTC0(9,0,0), /* move $9 to COP0 [cp0_reg select] */ + + MIPS32_LW(9,0,15), /* lw $9,($15) */ + MIPS32_LW(8,0,15), /* lw $8,($15) */ + MIPS32_B(NEG16(12)), /* b start */ + MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + }; + + /** + * Note that MIPS32_MTC0 macro is implemented via MIPS32_R_INST macro. + * In order to insert our parameters, we must change rd and funct fields. + */ + code[8] |= (cp0_reg << 11) | cp0_sel; /* change rd and funct fields of MIPS32_R_INST macro */ + + /* TODO remove array */ + uint32_t *param_in = malloc(1 * sizeof(uint32_t)); + int retval; + param_in[0] = val; + + retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 1, param_in, 0, NULL, 1); + + free(param_in); + + return retval; +} + +/** + * \b mips32_pracc_sync_cache + * + * Synchronize Caches to Make Instruction Writes Effective + * (ref. doc. MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set, + * Document Number: MD00086, Revision 2.00, June 9, 2003) + * + * When the instruction stream is written, the SYNCI instruction should be used + * in conjunction with other instructions to make the newly-written instructions effective. + * + * Explanation : + * A program that loads another program into memory is actually writing the D- side cache. + * The instructions it has loaded can't be executed until they reach the I-cache. + * + * After the instructions have been written, the loader should arrange + * to write back any containing D-cache line and invalidate any locations + * already in the I-cache. + * + * You can do that with cache instructions, but those instructions are only available in kernel mode, + * and a loader writing instructions for the use of its own process need not be privileged software. + * + * In the latest MIPS32/64 CPUs, MIPS provides the synci instruction, + * which does the whole job for a cache-line-sized chunk of the memory you just loaded: + * That is, it arranges a D-cache write-back and an I-cache invalidate. + * + * To employ synci at user level, you need to know the size of a cache line, + * and that can be obtained with a rdhwr SYNCI_Step + * from one of the standard “hardware registers”. + */ +static int mips32_pracc_sync_cache(struct mips_ejtag *ejtag_info, + uint32_t start_addr, uint32_t end_addr) +{ + static const uint32_t code[] = { + /* start: */ + MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(8,0,15), /* sw $8,($15) */ + MIPS32_SW(9,0,15), /* sw $9,($15) */ + MIPS32_SW(10,0,15), /* sw $10,($15) */ + MIPS32_SW(11,0,15), /* sw $11,($15) */ + + MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ + MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), + MIPS32_LW(9,0,8), /* Load write start_addr to $9 */ + MIPS32_LW(10,4,8), /* Load write end_addr to $10 */ + + MIPS32_RDHWR(11, MIPS32_SYNCI_STEP), /* $11 = MIPS32_SYNCI_STEP */ + MIPS32_BEQ(11,0,6), /* beq $11, $0, end */ + MIPS32_NOP, + /* synci_loop : */ + MIPS32_SYNCI(0,9), /* synci 0($9) */ + MIPS32_SLTU(8,10,9), /* sltu $8, $10, $9 # $8 = $10 < $9 ? 1 : 0 */ + MIPS32_BNE(8,0,NEG16(3)), /* bne $8, $0, synci_loop */ + MIPS32_ADDU(9, 9, 11), /* $9 += MIPS32_SYNCI_STEP */ + MIPS32_SYNC, + /* end: */ + MIPS32_LW(11,0,15), /* lw $11,($15) */ + MIPS32_LW(10,0,15), /* lw $10,($15) */ + MIPS32_LW(9,0,15), /* lw $9,($15) */ + MIPS32_LW(8,0,15), /* lw $8,($15) */ + MIPS32_B(NEG16(24)), /* b start */ + MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + }; + + /* TODO remove array */ + uint32_t *param_in = malloc(2 * sizeof(uint32_t)); + int retval; + param_in[0] = start_addr; + param_in[1] = end_addr; + + retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 2, param_in, 0, NULL, 1); + + free(param_in); + + return retval; +} + +/** + * \b mips32_pracc_clean_invalidate_cache + * + * Writeback D$ and Invalidate I$ + * so that the instructions written can be visible to CPU + */ +static int mips32_pracc_clean_invalidate_cache(struct mips_ejtag *ejtag_info, + uint32_t start_addr, uint32_t end_addr) +{ + static const uint32_t code[] = { + /* start: */ + MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ + MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */ + MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)), + MIPS32_SW(8,0,15), /* sw $8,($15) */ + MIPS32_SW(9,0,15), /* sw $9,($15) */ + MIPS32_SW(10,0,15), /* sw $10,($15) */ + MIPS32_SW(11,0,15), /* sw $11,($15) */ + + MIPS32_LUI(8,UPPER16(MIPS32_PRACC_PARAM_IN)), /* $8 = MIPS32_PRACC_PARAM_IN */ + MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_PARAM_IN)), + MIPS32_LW(9,0,8), /* Load write start_addr to $9 */ + MIPS32_LW(10,4,8), /* Load write end_addr to $10 */ + MIPS32_LW(11,8,8), /* Load write clsiz to $11 */ + + /* cache_loop: */ + MIPS32_SLTU(8,10,9), /* sltu $8, $10, $9 : $8 <- $10 < $9 ? */ + MIPS32_BGTZ(8,6), /* bgtz $8, end */ + MIPS32_NOP, + + MIPS32_CACHE(MIPS32_CACHE_D_HIT_WRITEBACK,0,9), /* cache Hit_Writeback_D, 0($9) */ + MIPS32_CACHE(MIPS32_CACHE_I_HIT_INVALIDATE,0,9), /* cache Hit_Invalidate_I, 0($9) */ + + MIPS32_ADDU(9,9,11), /* $9 += $11 */ + + MIPS32_B(NEG16(7)), /* b cache_loop */ + MIPS32_NOP, + /* end: */ + MIPS32_LW(11,0,15), /* lw $11,($15) */ + MIPS32_LW(10,0,15), /* lw $10,($15) */ + MIPS32_LW(9,0,15), /* lw $9,($15) */ + MIPS32_LW(8,0,15), /* lw $8,($15) */ + MIPS32_B(NEG16(25)), /* b start */ + MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ + }; + + /** + * Find cache line size in bytes + */ + uint32_t conf; + uint32_t dl, clsiz; + + mips32_cp0_read(ejtag_info, &conf, 16, 1); + dl = (conf & MIPS32_CONFIG1_DL_MASK) >> MIPS32_CONFIG1_DL_SHIFT; + + /* dl encoding : dl=1 => 4 bytes, dl=2 => 8 bytes, etc... */ + clsiz = 0x2 << dl; + + /* TODO remove array */ + uint32_t *param_in = malloc(3 * sizeof(uint32_t)); + int retval; + param_in[0] = start_addr; + param_in[1] = end_addr; + param_in[2] = clsiz; + + retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 3, param_in, 0, NULL, 1); + + free(param_in); + + return retval; } + int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf) { + int retval; + switch (size) { case 1: - return mips32_pracc_write_mem8(ejtag_info, addr, count, (uint8_t*)buf); + retval = mips32_pracc_write_mem8(ejtag_info, addr, count, (uint8_t*)buf); + break; case 2: - return mips32_pracc_write_mem16(ejtag_info, addr, count,(uint16_t*)buf); + retval = mips32_pracc_write_mem16(ejtag_info, addr, count,(uint16_t*)buf); + break; case 4: if (count == 1) - return mips32_pracc_write_u32(ejtag_info, addr, (uint32_t*)buf); + { + retval = mips32_pracc_write_u32(ejtag_info, addr, (uint32_t*)buf); + } else - return mips32_pracc_write_mem32(ejtag_info, addr, count, (uint32_t*)buf); + { + retval = mips32_pracc_write_mem32(ejtag_info, addr, count, (uint32_t*)buf); + } + break; + default: + retval = ERROR_FAIL; } - return ERROR_OK; + /** + * If we are in the cachable regoion and cache is activated, + * we must clean D$ + invalidate I$ after we did the write, + * so that changes do not continue to live only in D$, but to be + * replicated in I$ also (maybe we wrote the istructions) + */ + uint32_t conf = 0; + int cached = 0; + + mips32_cp0_read(ejtag_info, &conf, 16, 0); + + switch (KSEGX(addr)) + { + case KUSEG: + cached = (conf & MIPS32_CONFIG0_KU_MASK) >> MIPS32_CONFIG0_KU_SHIFT; + break; + case KSEG0 : + cached = (conf & MIPS32_CONFIG0_K0_MASK) >> MIPS32_CONFIG0_K0_SHIFT; + break; + case KSEG1: + /* uncachable segment - nothing to do */ + break; + case KSEG2: + case KSEG3: + cached = (conf & MIPS32_CONFIG0_K23_MASK) >> MIPS32_CONFIG0_K23_SHIFT; + break; + default: + /* what ? */ + break; + } + + /** + * Check cachablitiy bits coherency algorithm - + * is the region cacheable or uncached. + * If cacheable we have to synchronize the cache + */ + if (cached == 0x3) + { + uint32_t start_addr, end_addr; + uint32_t rel; + + start_addr = addr; + end_addr = addr + count * size; + + /** select cache synchronisation mechanism based on Architecture Release */ + rel = (conf & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT; + switch (rel) + { + case MIPS32_ARCH_REL1 : + /* MIPS32/64 Release 1 - we must use cache instruction */ + mips32_pracc_clean_invalidate_cache(ejtag_info, start_addr, end_addr); + break; + case MIPS32_ARCH_REL2 : + /* MIPS32/64 Release 2 - we can use synci instruction */ + mips32_pracc_sync_cache(ejtag_info, start_addr, end_addr); + break; + default : + /* what ? */ + break; + } + } + + return retval; } -int mips32_pracc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf) +static int mips32_pracc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf) { static const uint32_t code[] = { /* start: */ @@ -599,15 +951,16 @@ int mips32_pracc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int c memcpy(¶m_in[2], buf, count * sizeof(uint32_t)); - mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \ + int retval; + retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, count + 2, param_in, 0, NULL, 1); free(param_in); - return ERROR_OK; + return retval; } -int mips32_pracc_write_u32(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *buf) +static int mips32_pracc_write_u32(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *buf) { static const uint32_t code[] = { /* start: */ @@ -633,13 +986,11 @@ int mips32_pracc_write_u32(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_ param_in[0] = addr; param_in[1] = *buf; - mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \ + return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, ARRAY_SIZE(param_in), param_in, 0, NULL, 1); - - return ERROR_OK; } -int mips32_pracc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf) +static int mips32_pracc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf) { static const uint32_t code[] = { /* start: */ @@ -689,15 +1040,16 @@ int mips32_pracc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int c param_in[i + 2] = buf[i]; } - mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \ + int retval; + retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, count + 2, param_in, 0, NULL, 1); free(param_in); - return ERROR_OK; + return retval; } -int mips32_pracc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf) +static int mips32_pracc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf) { static const uint32_t code[] = { /* start: */ @@ -748,7 +1100,7 @@ int mips32_pracc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int co param_in[i + 2] = buf[i]; } - retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \ + retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, count + 2, param_in, 0, NULL, 1); free(param_in); @@ -810,7 +1162,7 @@ int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs) MIPS32_LW(2,36*4,1), /* lw $2,36*4($1) */ MIPS32_MTC0(2,13,0), /* move $2 to cause*/ MIPS32_LW(2,37*4,1), /* lw $2,37*4($1) */ - MIPS32_MTC0(2,24,0), /* move $2 to pc */ + MIPS32_MTC0(2,24,0), /* move $2 to depc (pc) */ MIPS32_LW(2,2*4,1), /* lw $2,2*4($1) */ MIPS32_LW(1,0,15), /* lw $1,($15) */ @@ -820,7 +1172,7 @@ int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs) int retval; - retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \ + retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, MIPS32NUMCOREREGS, regs, 0, NULL, 1); return retval; @@ -884,7 +1236,7 @@ int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs) MIPS32_SW(2,35*4,1), /* sw $2,35*4($1) */ MIPS32_MFC0(2,13,0), /* move cause to $2 */ MIPS32_SW(2,36*4,1), /* sw $2,36*4($1) */ - MIPS32_MFC0(2,24,0), /* move pc to $2 */ + MIPS32_MFC0(2,24,0), /* move depc (pc) to $2 */ MIPS32_SW(2,37*4,1), /* sw $2,37*4($1) */ MIPS32_LW(2,0,15), /* lw $2,($15) */ @@ -895,7 +1247,7 @@ int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs) int retval; - retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, \ + retval = mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code, 0, NULL, MIPS32NUMCOREREGS, regs, 1); return retval; @@ -909,7 +1261,7 @@ int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs) * 3. data ... */ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source, - int write, uint32_t addr, int count, uint32_t *buf) + int write_t, uint32_t addr, int count, uint32_t *buf) { uint32_t handler_code[] = { /* caution when editing, table is modified below */ @@ -954,7 +1306,7 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are if (source->size < MIPS32_FASTDATA_HANDLER_SIZE) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - if (write) + if (write_t) { handler_code[8] = MIPS32_LW(11,0,8); /* load data from probe at fastdata area */ handler_code[9] = MIPS32_SW(11,0,9); /* store data to RAM @ r9 */ @@ -966,9 +1318,14 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are } /* write program into RAM */ - mips32_pracc_write_mem32(ejtag_info, source->address, ARRAY_SIZE(handler_code), handler_code); + if (write_t != ejtag_info->fast_access_save) + { + mips32_pracc_write_mem32(ejtag_info, source->address, ARRAY_SIZE(handler_code), handler_code); + /* save previous operation to speed to any consecutive read/writes */ + ejtag_info->fast_access_save = write_t; + } - LOG_DEBUG("%s using 0x%.8x for write handler\n", __func__, source->address); + LOG_DEBUG("%s using 0x%.8" PRIx32 " for write handler", __func__, source->address); jmp_code[1] |= UPPER16(source->address); jmp_code[2] |= LOWER16(source->address); @@ -978,13 +1335,13 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) return retval; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); - mips_ejtag_drscan_32(ejtag_info, &jmp_code[i]); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA); + mips_ejtag_drscan_32_out(ejtag_info, jmp_code[i]); /* Clear the access pending bit (let the processor eat!) */ ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); - mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); + mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl); } if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) @@ -992,26 +1349,30 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are /* next fetch to dmseg should be in FASTDATA_AREA, check */ address = 0; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); - mips_ejtag_drscan_32(ejtag_info, &address); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); + retval = mips_ejtag_drscan_32(ejtag_info, &address); + if (retval != ERROR_OK) + return retval; if (address != MIPS32_PRACC_FASTDATA_AREA) return ERROR_FAIL; + /* wait PrAcc pending bit for FASTDATA write */ + if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) + return retval; + /* Send the load start address */ val = addr; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA, NULL); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA); mips_ejtag_fastdata_scan(ejtag_info, 1, &val); /* Send the load end address */ val = addr + (count - 1) * 4; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA, NULL); mips_ejtag_fastdata_scan(ejtag_info, 1, &val); for (i = 0; i < count; i++) { - /* Send the data out using fastdata (clears the access pending bit) */ - if ((retval = mips_ejtag_fastdata_scan(ejtag_info, write, buf++)) != ERROR_OK) + if ((retval = mips_ejtag_fastdata_scan(ejtag_info, write_t, buf++)) != ERROR_OK) return retval; } @@ -1025,11 +1386,13 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are return retval; address = 0; - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); - mips_ejtag_drscan_32(ejtag_info, &address); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS); + retval = mips_ejtag_drscan_32(ejtag_info, &address); + if (retval != ERROR_OK) + return retval; if (address != MIPS32_PRACC_TEXT) - LOG_ERROR("mini program did not return to start\n"); + LOG_ERROR("mini program did not return to start"); return retval; }