X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fmips_ejtag.c;h=e0550a81a442b136f9f4b16b26d95ab69e7173ef;hb=57d7743639d5092770d79f7c4b12ae694c482750;hp=bebad9ace3de3785c7565cc3a06d2357769a0abf;hpb=f6412d9c7b22ab25caec6be19317f0fc4a840fdd;p=openocd.git

diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index bebad9ace3..e0550a81a4 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -28,7 +28,6 @@
 #include "mips32.h"
 #include "mips_ejtag.h"
 
-
 int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr, void *delete_me_and_submit_patch)
 {
 	struct jtag_tap *tap;
@@ -42,13 +41,12 @@ int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr, void *del
 		struct scan_field field;
 		uint8_t t[4];
 
-		field.tap = tap;
 		field.num_bits = tap->ir_length;
 		field.out_value = t;
 		buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
 		field.in_value = NULL;
 
-		jtag_add_ir_scan(1, &field, jtag_get_end_state());
+		jtag_add_ir_scan(tap, &field, jtag_get_end_state());
 	}
 
 	return ERROR_OK;
@@ -62,12 +60,11 @@ int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
 
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL);
 
-	field.tap = ejtag_info->tap;
 	field.num_bits = 32;
 	field.out_value = NULL;
 	field.in_value = (void*)idcode;
 
-	jtag_add_dr_scan(1, &field, jtag_get_end_state());
+	jtag_add_dr_scan(ejtag_info->tap, 1, &field, jtag_get_end_state());
 
 	if (jtag_execute_queue() != ERROR_OK)
 	{
@@ -85,12 +82,11 @@ int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
 
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL);
 
-	field.tap = ejtag_info->tap;
 	field.num_bits = 32;
 	field.out_value = NULL;
 	field.in_value = (void*)impcode;
 
-	jtag_add_dr_scan(1, &field, jtag_get_end_state());
+	jtag_add_dr_scan(ejtag_info->tap, 1, &field, jtag_get_end_state());
 
 	if (jtag_execute_queue() != ERROR_OK)
 	{
@@ -111,13 +107,12 @@ int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
 	uint8_t t[4], r[4];
 	int retval;
 
-	field.tap = tap;
 	field.num_bits = 32;
 	field.out_value = t;
 	buf_set_u32(field.out_value, 0, field.num_bits, *data);
 	field.in_value = r;
 
-	jtag_add_dr_scan(1, &field, jtag_get_end_state());
+	jtag_add_dr_scan(tap, 1, &field, jtag_get_end_state());
 
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
@@ -152,12 +147,12 @@ int mips_ejtag_step_disable(struct mips_ejtag *ejtag_info)
 {
 	uint32_t code[] = {
 			MIPS32_MTC0(15,31,0),							/* move $15 to COP0 DeSave */
-			MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), 	/* $15 = MIPS32_PRACC_STACK */
+			MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)),		/* $15 = MIPS32_PRACC_STACK */
 			MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
-			MIPS32_SW(1,0,15), 								/* sw $1,($15) */
-			MIPS32_SW(2,0,15), 								/* sw $2,($15) */
+			MIPS32_SW(1,0,15),								/* sw $1,($15) */
+			MIPS32_SW(2,0,15),								/* sw $2,($15) */
 			MIPS32_MFC0(1,23,0),							/* move COP0 Debug to $1 */
-			MIPS32_LUI(2,0xFFFF), 							/* $2 = 0xfffffeff */
+			MIPS32_LUI(2,0xFFFF),							/* $2 = 0xfffffeff */
 			MIPS32_ORI(2,2,0xFEFF),
 			MIPS32_AND(1,1,2),
 			MIPS32_MTC0(1,23,0),							/* move $1 to COP0 Debug */
@@ -216,11 +211,11 @@ int mips_ejtag_read_debug(struct mips_ejtag *ejtag_info, uint32_t* debug_reg)
 	/* read ejtag ECR */
 	uint32_t code[] = {
 			MIPS32_MTC0(15,31,0),							/* move $15 to COP0 DeSave */
-			MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)), 	/* $15 = MIPS32_PRACC_STACK */
+			MIPS32_LUI(15,UPPER16(MIPS32_PRACC_STACK)),		/* $15 = MIPS32_PRACC_STACK */
 			MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_STACK)),
-			MIPS32_SW(1,0,15), 								/* sw $1,($15) */
-			MIPS32_SW(2,0,15), 								/* sw $2,($15) */
-			MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_OUT)), 	/* $1 = MIPS32_PRACC_PARAM_OUT */
+			MIPS32_SW(1,0,15),								/* sw $1,($15) */
+			MIPS32_SW(2,0,15),								/* sw $2,($15) */
+			MIPS32_LUI(1,UPPER16(MIPS32_PRACC_PARAM_OUT)),	/* $1 = MIPS32_PRACC_PARAM_OUT */
 			MIPS32_ORI(1,1,LOWER16(MIPS32_PRACC_PARAM_OUT)),
 			MIPS32_MFC0(2,23,0),							/* move COP0 Debug to $2 */
 			MIPS32_SW(2,0,1),
@@ -265,16 +260,15 @@ int mips_ejtag_init(struct mips_ejtag *ejtag_info)
 			break;
 	}
 	LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
-		ejtag_info->impcode & (1 << 28) ? " R3k":    " R4k",
-		ejtag_info->impcode & (1 << 24) ? " DINT":   "",
-		ejtag_info->impcode & (1 << 22) ? " ASID_8": "",
-		ejtag_info->impcode & (1 << 21) ? " ASID_6": "",
-		ejtag_info->impcode & (1 << 16) ? " MIPS16": "",
-		ejtag_info->impcode & (1 << 14) ? " noDMA":  " DMA",
-		ejtag_info->impcode & (1 << 0)  ? " MIPS64": " MIPS32"
-);
-
-	if ((ejtag_info->impcode & (1 << 14)) == 0)
+		ejtag_info->impcode & EJTAG_IMP_R3K ? " R3k" : " R4k",
+		ejtag_info->impcode & EJTAG_IMP_DINT ? " DINT" : "",
+		ejtag_info->impcode & (1 << 22) ? " ASID_8" : "",
+		ejtag_info->impcode & (1 << 21) ? " ASID_6" : "",
+		ejtag_info->impcode & EJTAG_IMP_MIPS16 ? " MIPS16" : "",
+		ejtag_info->impcode & EJTAG_IMP_NODMA ? " noDMA" : " DMA",
+		ejtag_info->impcode & EJTAG_DCR_MIPS64  ? " MIPS64" : " MIPS32");
+
+	if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0)
 		LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
 
 	/* set initial state for ejtag control reg */
@@ -296,13 +290,11 @@ int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write, uint32_t
 	uint8_t t[4] = {0, 0, 0, 0};
 
 	/* fastdata 1-bit register */
-	fields[0].tap = tap;
 	fields[0].num_bits = 1;
 	fields[0].out_value = &spracc;
 	fields[0].in_value = NULL;
 
 	/* processor access data register 32 bit */
-	fields[1].tap = tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = t;
 
@@ -316,7 +308,7 @@ int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write, uint32_t
 		fields[1].in_value = (uint8_t *) data;
 	}
 
-	jtag_add_dr_scan(2, fields, jtag_get_end_state());
+	jtag_add_dr_scan(tap, 2, fields, jtag_get_end_state());
 	keep_alive();
 
 	return ERROR_OK;