X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fmips_m4k.c;h=6109869484a7b4865d611f2655537903b8e109e7;hb=c0787b699496080d48174713a0b30e81ef5db3be;hp=e89ee844cd9587bef4fb91691ffc1bccb80a41ed;hpb=3a4896182036eb472a06f66be3710d5c228b6748;p=openocd.git diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index e89ee844cd..6109869484 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -25,6 +25,7 @@ #include "mips32.h" #include "mips_m4k.h" +#include "mips32_dmaacc.h" #include "jtag.h" #include "log.h" @@ -43,8 +44,8 @@ int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 cou int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int mips_m4k_register_commands(struct command_context_s *cmd_ctx); int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int mips_m4k_quit(); -int mips_m4k_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target); +int mips_m4k_quit(void); +int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp); int mips_m4k_examine(struct target_s *target); int mips_m4k_assert_reset(target_t *target); @@ -83,7 +84,7 @@ target_type_t mips_m4k_target = .remove_watchpoint = mips_m4k_remove_watchpoint, .register_commands = mips_m4k_register_commands, - .target_command = mips_m4k_target_command, + .target_create = mips_m4k_target_create, .init_target = mips_m4k_init_target, .examine = mips_m4k_examine, .quit = mips_m4k_quit @@ -119,8 +120,9 @@ int mips_m4k_debug_entry(target_t *target) mips32_save_context(target); - LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s", \ - *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value), target_state_strings[target->state]); + LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s", + *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value), + Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); return ERROR_OK; } @@ -130,13 +132,29 @@ int mips_m4k_poll(target_t *target) int retval; mips32_common_t *mips32 = target->arch_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info; + u32 ejtag_ctrl = ejtag_info->ejtag_ctrl; /* read ejtag control reg */ jtag_add_end_state(TAP_RTI); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); - mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl); + mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - if (ejtag_info->ejtag_ctrl & EJTAG_CTRL_BRKST) + /* clear this bit before handling polling + * as after reset registers will read zero */ + if (ejtag_ctrl & EJTAG_CTRL_ROCC) + { + /* we have detected a reset, clear flag + * otherwise ejtag will not work */ + jtag_add_end_state(TAP_RTI); + ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC; + + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); + LOG_DEBUG("Reset Detected"); + } + + /* check for processor halted */ + if (ejtag_ctrl & EJTAG_CTRL_BRKST) { if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) { @@ -165,19 +183,7 @@ int mips_m4k_poll(target_t *target) target->state = TARGET_RUNNING; } - if (ejtag_info->ejtag_ctrl & EJTAG_CTRL_ROCC) - { - /* we have detected a reset, clear flag - * otherwise ejtag will not work */ - jtag_add_end_state(TAP_RTI); - ejtag_info->ejtag_ctrl &= ~EJTAG_CTRL_ROCC; - - mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); - mips_ejtag_drscan_32(ejtag_info, &ejtag_info->ejtag_ctrl); - LOG_DEBUG("Reset Detected"); - } - -// LOG_DEBUG("ctrl=0x%08X", ejtag_info->ejtag_ctrl); +// LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl); return ERROR_OK; } @@ -187,7 +193,8 @@ int mips_m4k_halt(struct target_s *target) mips32_common_t *mips32 = target->arch_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info; - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); if (target->state == TARGET_HALTED) { @@ -230,8 +237,10 @@ int mips_m4k_assert_reset(target_t *target) { mips32_common_t *mips32 = target->arch_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info; + mips_m4k_common_t *mips_m4k = mips32->arch_info; - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); if (!(jtag_reset_config & RESET_HAS_SRST)) { @@ -251,14 +260,24 @@ int mips_m4k_assert_reset(target_t *target) mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL); } - /* here we should issue a srst only, but we may have to assert trst as well */ - if (jtag_reset_config & RESET_SRST_PULLS_TRST) + if (strcmp(mips_m4k->variant, "ejtag_srst") == 0) { - jtag_add_reset(1, 1); + u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST; + LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor..."); + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); + mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); } else { - jtag_add_reset(0, 1); + /* here we should issue a srst only, but we may have to assert trst as well */ + if (jtag_reset_config & RESET_SRST_PULLS_TRST) + { + jtag_add_reset(1, 1); + } + else + { + jtag_add_reset(0, 1); + } } target->state = TARGET_RESET; @@ -266,12 +285,20 @@ int mips_m4k_assert_reset(target_t *target) mips32_invalidate_core_regs(target); + if (target->reset_halt) + { + int retval; + if ((retval = target_halt(target))!=ERROR_OK) + return retval; + } + return ERROR_OK; } int mips_m4k_deassert_reset(target_t *target) { - LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", + Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); /* deassert reset lines */ jtag_add_reset(0, 0); @@ -306,7 +333,7 @@ int mips_m4k_resume(struct target_s *target, int current, u32 address, int handl } /* current = 1: continue on current pc, otherwise continue at
*/ - if (!current) + if (!current) { buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address); mips32->core_cache->reg_list[MIPS32_PC].dirty = 1; @@ -500,7 +527,11 @@ int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 cou case 4: case 2: case 1: - return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer); + /* if noDMA off, use DMAACC mode for memory read */ + if(ejtag_info->impcode & EJTAG_IMP_NODMA) + return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer); + else + return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer); default: LOG_ERROR("BUG: we shouldn't get here"); exit(-1); @@ -535,7 +566,11 @@ int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 co case 4: case 2: case 1: - mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer); + /* if noDMA off, use DMAACC mode for memory write */ + if(ejtag_info->impcode & EJTAG_IMP_NODMA) + mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer); + else + mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer); break; default: LOG_ERROR("BUG: we shouldn't get here"); @@ -561,12 +596,12 @@ int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *tar return ERROR_OK; } -int mips_m4k_quit() +int mips_m4k_quit(void) { return ERROR_OK; } -int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, int chain_pos, char *variant) +int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, int chain_pos, const char *variant) { mips32_common_t *mips32 = &mips_m4k->mips32_common; @@ -584,28 +619,15 @@ int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, int c /* initialize mips4k specific info */ mips32_init_arch_info(target, mips32, chain_pos, variant); mips32->arch_info = mips_m4k; - + return ERROR_OK; } -int mips_m4k_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target) +int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp) { - int chain_pos; - char *variant = NULL; - mips_m4k_common_t *mips_m4k = malloc(sizeof(mips_m4k_common_t)); - - if (argc < 4) - { - LOG_ERROR("'target mips4k' requires at least one additional argument"); - exit(-1); - } - - chain_pos = strtoul(args[3], NULL, 0); - - if (argc >= 5) - variant = args[4]; + mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t)); - mips_m4k_init_arch_info(target, mips_m4k, chain_pos, variant); + mips_m4k_init_arch_info(target, mips_m4k, target->chain_position, target->variant); return ERROR_OK; }