X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fnds32_v2.c;h=ac2aad0b85931f10b1e4ffcf73c9006b32187c7e;hb=a6c4eb03455f6e97fc25183aae249d6ccdcbfb0f;hp=ceeed0af35624f1d243b3f3d1068eee34189692d;hpb=cd0ef0cd3f738a8e1b81cfc06b8ec46345f970f0;p=openocd.git

diff --git a/src/target/nds32_v2.c b/src/target/nds32_v2.c
index ceeed0af35..ac2aad0b85 100644
--- a/src/target/nds32_v2.c
+++ b/src/target/nds32_v2.c
@@ -114,7 +114,7 @@ static int nds32_v2_activate_hardware_breakpoint(struct target *target)
 				/* enable breakpoint (physical address) */
 				aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0xA);
 
-			LOG_DEBUG("Add hardware BP %d at %08" PRIx32, hbr_index,
+			LOG_DEBUG("Add hardware BP %" PRId32 " at %08" PRIx32, hbr_index,
 					bp->address);
 
 			hbr_index++;
@@ -141,7 +141,7 @@ static int nds32_v2_deactivate_hardware_breakpoint(struct target *target)
 		else
 			return ERROR_FAIL;
 
-		LOG_DEBUG("Remove hardware BP %d at %08" PRIx32, hbr_index,
+		LOG_DEBUG("Remove hardware BP %" PRId32 " at %08" PRIx32, hbr_index,
 				bp->address);
 
 		hbr_index++;
@@ -186,7 +186,7 @@ static int nds32_v2_activate_hardware_watchpoint(struct target *target)
 		/* set value */
 		aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + wp_num, 0);
 
-		LOG_DEBUG("Add hardware wathcpoint %d at %08" PRIx32 " mask %08" PRIx32, wp_num,
+		LOG_DEBUG("Add hardware wathcpoint %" PRId32 " at %08" PRIx32 " mask %08" PRIx32, wp_num,
 				wp->address, wp->mask);
 
 	}
@@ -206,7 +206,7 @@ static int nds32_v2_deactivate_hardware_watchpoint(struct target *target)
 		/* disable watchpoint */
 		aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, 0x0);
 
-		LOG_DEBUG("Remove hardware wathcpoint %d at %08" PRIx32 " mask %08" PRIx32,
+		LOG_DEBUG("Remove hardware wathcpoint %" PRId32 " at %08" PRIx32 " mask %08" PRIx32,
 				wp_num, wp->address, wp->mask);
 	}
 
@@ -231,7 +231,7 @@ static int nds32_v2_check_interrupt_stack(struct nds32_v2_common *nds32_v2)
 	nds32->current_interrupt_level = (val_ir0 >> 1) & 0x3;
 
 	if (nds32_reach_max_interrupt_level(nds32)) {
-		LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level %d. -->",
+		LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level %" PRIu32 ". -->",
 				nds32->current_interrupt_level);
 
 		/* decrease interrupt level */
@@ -287,8 +287,6 @@ static int nds32_v2_debug_entry(struct nds32 *nds32, bool enable_watchpoint)
 {
 	LOG_DEBUG("nds32_v2_debug_entry");
 
-	jtag_poll_set_enabled(false);
-
 	if (nds32->virtual_hosting)
 		LOG_WARNING("<-- TARGET WARNING! Virtual hosting is not supported "
 				"under V1/V2 architecture. -->");
@@ -387,29 +385,6 @@ static int nds32_v2_leave_debug_state(struct nds32 *nds32, bool enable_watchpoin
 
 	register_cache_invalidate(nds32->core_cache);
 
-	jtag_poll_set_enabled(true);
-
-	return ERROR_OK;
-}
-
-static int nds32_v2_soft_reset_halt(struct target *target)
-{
-	/* TODO: test it */
-	struct nds32 *nds32 = target_to_nds32(target);
-	struct aice_port_s *aice = target_to_aice(target);
-
-	aice_assert_srst(aice, AICE_SRST);
-
-	/* halt core and set pc to 0x0 */
-	int retval = target_halt(target);
-	if (retval != ERROR_OK)
-		return retval;
-
-	/* start fetching from IVB */
-	uint32_t value_ir3;
-	nds32_get_mapped_reg(nds32, IR3, &value_ir3);
-	nds32_set_mapped_reg(nds32, PC, value_ir3 & 0xFFFF0000);
-
 	return ERROR_OK;
 }
 
@@ -426,10 +401,6 @@ static int nds32_v2_deassert_reset(struct target *target)
 		retval = target_halt(target);
 		if (retval != ERROR_OK)
 			return retval;
-		/* call target_poll() to avoid "Halt timed out" */
-		CHECK_RETVAL(target_poll(target));
-	} else {
-		jtag_poll_set_enabled(false);
 	}
 
 	return ERROR_OK;
@@ -456,7 +427,7 @@ static int nds32_v2_add_breakpoint(struct target *target,
 			LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
 					"breakpoints/watchpoints!  The limit of "
 					"combined hardware breakpoints/watchpoints "
-					"is %d. -->", nds32_v2->n_hbr);
+					"is %" PRId32 ". -->", nds32_v2->n_hbr);
 			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 		}
 
@@ -515,7 +486,7 @@ static int nds32_v2_add_watchpoint(struct target *target,
 	if (nds32_v2->n_hbr <= nds32_v2->next_hbr_index) {
 		LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
 				"breakpoints/watchpoints!  The limit of "
-				"combined hardware breakpoints/watchpoints is %d. -->", nds32_v2->n_hbr);
+				"combined hardware breakpoints/watchpoints is %" PRId32 ". -->", nds32_v2->n_hbr);
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
@@ -655,7 +626,7 @@ static int nds32_v2_examine(struct target *target)
 
 	nds32_v2->next_hbr_index = 0;
 
-	LOG_INFO("%s: total hardware breakpoint %d", target_name(target),
+	LOG_INFO("%s: total hardware breakpoint %" PRId32, target_name(target),
 			nds32_v2->n_hbr);
 
 	nds32->target->state = TARGET_RUNNING;
@@ -782,7 +753,6 @@ struct target_type nds32_v2_target = {
 
 	.assert_reset = nds32_assert_reset,
 	.deassert_reset = nds32_v2_deassert_reset,
-	.soft_reset_halt = nds32_v2_soft_reset_halt,
 
 	/* register access */
 	.get_gdb_reg_list = nds32_get_gdb_reg_list,