X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fxscale.c;h=659caec18fecf9d6fdd8a6be8884ef62ae413206;hb=ff810723e051ed1f86cffcb565ade6b4d1fc50c8;hp=a4a8eabd6111dc92b70eda31c3fbeb08649def71;hpb=2861877b32a7a2f4022a1c3d9b66c9b4879878ac;p=openocd.git diff --git a/src/target/xscale.c b/src/target/xscale.c index a4a8eabd61..659caec18f 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -857,8 +857,8 @@ static int xscale_arch_state(struct target *target) "%s", armv4_5_state_strings[armv4_5->core_state], Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name , - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), + arm_mode_name(armv4_5->core_mode), + buf_get_u32(armv4_5->cpsr->value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), state[xscale->armv4_5_mmu.mmu_enabled], state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], @@ -948,19 +948,17 @@ static int xscale_debug_entry(struct target *target) LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]); } - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; + arm_set_cpsr(armv4_5, buffer[9]); LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]); - armv4_5->core_mode = buffer[9] & 0x1f; - if (armv4_5_mode_to_number(armv4_5->core_mode) == -1) + if (!is_arm_mode(armv4_5->core_mode)) { target->state = TARGET_UNKNOWN; LOG_ERROR("cpsr contains invalid mode value - communication failure"); return ERROR_TARGET_FAILURE; } - LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]); + LOG_DEBUG("target entered debug state in %s mode", + arm_mode_name(armv4_5->core_mode)); if (buffer[9] & 0x20) armv4_5->core_state = ARMV4_5_STATE_THUMB; @@ -968,9 +966,6 @@ static int xscale_debug_entry(struct target *target) armv4_5->core_state = ARMV4_5_STATE_ARM; - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) - return ERROR_FAIL; - /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */ if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS)) { @@ -1262,8 +1257,10 @@ static int xscale_resume(struct target *target, int current, xscale_send_u32(target, 0x30); /* send CPSR */ - xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + xscale_send_u32(target, + buf_get_u32(armv4_5->cpsr->value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, + buf_get_u32(armv4_5->cpsr->value, 0, 32)); for (i = 7; i >= 0; i--) { @@ -1305,8 +1302,9 @@ static int xscale_resume(struct target *target, int current, xscale_send_u32(target, 0x30); /* send CPSR */ - xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + xscale_send_u32(target, buf_get_u32(armv4_5->cpsr->value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, + buf_get_u32(armv4_5->cpsr->value, 0, 32)); for (i = 7; i >= 0; i--) { @@ -1324,7 +1322,7 @@ static int xscale_resume(struct target *target, int current, if (!debug_execution) { /* registers are now invalid */ - armv4_5_invalidate_core_regs(target); + register_cache_invalidate(armv4_5->core_cache); target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); } @@ -1383,9 +1381,12 @@ static int xscale_step_inner(struct target *target, int current, return retval; /* send CPSR */ - if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK) + retval = xscale_send_u32(target, + buf_get_u32(armv4_5->cpsr->value, 0, 32)); + if (retval != ERROR_OK) return retval; - LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, + buf_get_u32(armv4_5->cpsr->value, 0, 32)); for (i = 7; i >= 0; i--) { @@ -1403,8 +1404,7 @@ static int xscale_step_inner(struct target *target, int current, target_call_event_callbacks(target, TARGET_EVENT_RESUMED); /* registers are now invalid */ - if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK) - return retval; + register_cache_invalidate(armv4_5->core_cache); /* wait for and process debug entry */ if ((retval = xscale_debug_entry(target)) != ERROR_OK) @@ -1540,7 +1540,7 @@ static int xscale_deassert_reset(struct target *target) breakpoint = breakpoint->next; } - armv4_5_invalidate_core_regs(target); + register_cache_invalidate(xscale->armv4_5_common.core_cache); /* FIXME mark hardware watchpoints got unset too. Also, * at least some of the XScale registers are invalid... @@ -1649,16 +1649,18 @@ static int xscale_deassert_reset(struct target *target) return ERROR_OK; } -static int xscale_read_core_reg(struct target *target, int num, - enum armv4_5_mode mode) +static int xscale_read_core_reg(struct target *target, struct reg *r, + int num, enum armv4_5_mode mode) { + /** \todo add debug handler support for core register reads */ LOG_ERROR("not implemented"); return ERROR_OK; } -static int xscale_write_core_reg(struct target *target, int num, - enum armv4_5_mode mode, uint32_t value) +static int xscale_write_core_reg(struct target *target, struct reg *r, + int num, enum armv4_5_mode mode, uint32_t value) { + /** \todo add debug handler support for core register writes */ LOG_ERROR("not implemented"); return ERROR_OK; } @@ -2832,7 +2834,6 @@ static void xscale_build_reg_cache(struct target *target) int num_regs = sizeof(xscale_reg_arch_info) / sizeof(struct xscale_reg); (*cache_p) = armv4_5_build_reg_cache(target, armv4_5); - armv4_5->core_cache = (*cache_p); (*cache_p)->next = malloc(sizeof(struct reg_cache)); cache_p = &(*cache_p)->next; @@ -3132,16 +3133,13 @@ COMMAND_HANDLER(xscale_handle_mmu_command) if (CMD_ARGC >= 1) { - if (strcmp("enable", CMD_ARGV[0]) == 0) - { + bool enable; + COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable); + if (enable) xscale_enable_mmu_caches(target, 1, 0, 0); - xscale->armv4_5_mmu.mmu_enabled = 1; - } - else if (strcmp("disable", CMD_ARGV[0]) == 0) - { + else xscale_disable_mmu_caches(target, 1, 0, 0); - xscale->armv4_5_mmu.mmu_enabled = 0; - } + xscale->armv4_5_mmu.mmu_enabled = enable; } command_print(CMD_CTX, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled"); @@ -3153,10 +3151,8 @@ COMMAND_HANDLER(xscale_handle_idcache_command) { struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); - int icache = 0, dcache = 0; - int retval; - retval = xscale_verify_pointer(CMD_CTX, xscale); + int retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; @@ -3166,38 +3162,28 @@ COMMAND_HANDLER(xscale_handle_idcache_command) return ERROR_OK; } - if (strcmp(CMD_NAME, "icache") == 0) - icache = 1; - else if (strcmp(CMD_NAME, "dcache") == 0) - dcache = 1; + bool icache; + COMMAND_PARSE_BOOL(CMD_NAME, icache, "icache", "dcache"); if (CMD_ARGC >= 1) { - if (strcmp("enable", CMD_ARGV[0]) == 0) - { - xscale_enable_mmu_caches(target, 0, dcache, icache); - - if (icache) - xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 1; - else if (dcache) - xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 1; - } - else if (strcmp("disable", CMD_ARGV[0]) == 0) - { - xscale_disable_mmu_caches(target, 0, dcache, icache); - - if (icache) - xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; - else if (dcache) - xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; - } + bool enable; + COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable); + if (enable) + xscale_enable_mmu_caches(target, 1, 0, 0); + else + xscale_disable_mmu_caches(target, 1, 0, 0); + if (icache) + xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable; + else + xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable; } - if (icache) - command_print(CMD_CTX, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled"); - - if (dcache) - command_print(CMD_CTX, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled"); + bool enabled = icache ? + xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled : + xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled; + const char *msg = enabled ? "enabled" : "disabled"; + command_print(CMD_CTX, "%s %s", CMD_NAME, msg); return ERROR_OK; }