X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fxscale.c;h=ccb1de563d80aefa7f8439edc6674186728e69db;hb=892604bc7e6b332cf3b0bf6c2586cbd0f54ec8ef;hp=742dd257bb31c1c0c442bbff2d5be447c6639a40;hpb=a2df544fd9cb758163b049f389c5cc07e97e029f;p=openocd.git diff --git a/src/target/xscale.c b/src/target/xscale.c index 742dd257bb..ccb1de563d 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -62,7 +62,7 @@ static int xscale_resume(struct target *, int current, uint32_t address, int handle_breakpoints, int debug_execution); static int xscale_debug_entry(struct target *); -static int xscale_restore_context(struct target *); +static int xscale_restore_banked(struct target *); static int xscale_get_reg(struct reg *reg); static int xscale_set_reg(struct reg *reg, uint8_t *buf); static int xscale_set_breakpoint(struct target *, struct breakpoint *); @@ -134,8 +134,6 @@ static const struct xscale_reg xscale_reg_arch_info[] = {-1, NULL}, /* TXRXCTRL implicit access via JTAG */ }; -static int xscale_reg_arch_type = -1; - /* convenience wrapper to access XScale specific registers */ static int xscale_set_reg_u32(struct reg *reg, uint32_t value) { @@ -193,7 +191,8 @@ static int xscale_read_dcsr(struct target *target) uint8_t field2_check_mask = 0x1; jtag_set_end_state(TAP_DRPAUSE); - xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR); + xscale_jtag_set_instr(target->tap, + XSCALE_SELDCSR << xscale->xscale_variant); buf_set_u32(&field0, 1, 1, xscale->hold_rst); buf_set_u32(&field0, 2, 1, xscale->external_debug_break); @@ -258,6 +257,7 @@ static int xscale_receive(struct target *target, uint32_t *buffer, int num_words if (num_words == 0) return ERROR_INVALID_ARGUMENTS; + struct xscale_common *xscale = target_to_xscale(target); int retval = ERROR_OK; tap_state_t path[3]; struct scan_field fields[3]; @@ -291,7 +291,8 @@ static int xscale_receive(struct target *target, uint32_t *buffer, int num_words fields[2].check_mask = &field2_check_mask; jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(target->tap, XSCALE_DBGTX); + xscale_jtag_set_instr(target->tap, + XSCALE_DBGTX << xscale->xscale_variant); jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */ /* repeat until all words have been collected */ @@ -373,7 +374,8 @@ static int xscale_read_tx(struct target *target, int consume) jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(target->tap, XSCALE_DBGTX); + xscale_jtag_set_instr(target->tap, + XSCALE_DBGTX << xscale->xscale_variant); path[0] = TAP_DRSELECT; path[1] = TAP_DRCAPTURE; @@ -414,7 +416,7 @@ static int xscale_read_tx(struct target *target, int consume) jtag_add_pathmove(3, path); else { - jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path); + jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path); } jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE)); @@ -471,7 +473,8 @@ static int xscale_write_rx(struct target *target) jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(target->tap, XSCALE_DBGRX); + xscale_jtag_set_instr(target->tap, + XSCALE_DBGRX << xscale->xscale_variant); memset(&fields, 0, sizeof fields); @@ -543,6 +546,7 @@ static int xscale_write_rx(struct target *target) /* send count elements of size byte to the debug handler */ static int xscale_send(struct target *target, uint8_t *buffer, int count, int size) { + struct xscale_common *xscale = target_to_xscale(target); uint32_t t[3]; int bits[3]; int retval; @@ -550,7 +554,8 @@ static int xscale_send(struct target *target, uint8_t *buffer, int count, int si jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(target->tap, XSCALE_DBGRX); + xscale_jtag_set_instr(target->tap, + XSCALE_DBGRX << xscale->xscale_variant); bits[0]=3; t[0]=0; @@ -631,7 +636,8 @@ static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_br xscale->external_debug_break = ext_dbg_brk; jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR); + xscale_jtag_set_instr(target->tap, + XSCALE_SELDCSR << xscale->xscale_variant); buf_set_u32(&field0, 1, 1, xscale->hold_rst); buf_set_u32(&field0, 2, 1, xscale->external_debug_break); @@ -685,6 +691,7 @@ static unsigned int parity (unsigned int v) static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8]) { + struct xscale_common *xscale = target_to_xscale(target); uint8_t packet[4]; uint8_t cmd; int word; @@ -694,7 +701,8 @@ static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8] /* LDIC into IR */ jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(target->tap, XSCALE_LDIC); + xscale_jtag_set_instr(target->tap, + XSCALE_LDIC << xscale->xscale_variant); /* CMD is b011 to load a cacheline into the Mini ICache. * Loading into the main ICache is deprecated, and unused. @@ -740,12 +748,14 @@ static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8] static int xscale_invalidate_ic_line(struct target *target, uint32_t va) { + struct xscale_common *xscale = target_to_xscale(target); uint8_t packet[4]; uint8_t cmd; struct scan_field fields[2]; jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(target->tap, XSCALE_LDIC); + xscale_jtag_set_instr(target->tap, + XSCALE_LDIC << xscale->xscale_variant); /* CMD for invalidate IC line b000, bits [6:4] b000 */ buf_set_u32(&cmd, 0, 6, 0x0); @@ -835,7 +845,7 @@ static int xscale_update_vectors(struct target *target) static int xscale_arch_state(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); - struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + struct arm *armv4_5 = &xscale->armv4_5_common; static const char *state[] = { @@ -859,8 +869,8 @@ static int xscale_arch_state(struct target *target) "%s", armv4_5_state_strings[armv4_5->core_state], Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name , - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), + arm_mode_name(armv4_5->core_mode), + buf_get_u32(armv4_5->cpsr->value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), state[xscale->armv4_5_mmu.mmu_enabled], state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], @@ -913,7 +923,7 @@ static int xscale_poll(struct target *target) static int xscale_debug_entry(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); - struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + struct arm *armv4_5 = &xscale->armv4_5_common; uint32_t pc; uint32_t buffer[10]; int i; @@ -950,36 +960,24 @@ static int xscale_debug_entry(struct target *target) LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]); } - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; + arm_set_cpsr(armv4_5, buffer[9]); LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]); - armv4_5->core_mode = buffer[9] & 0x1f; - if (armv4_5_mode_to_number(armv4_5->core_mode) == -1) + if (!is_arm_mode(armv4_5->core_mode)) { target->state = TARGET_UNKNOWN; LOG_ERROR("cpsr contains invalid mode value - communication failure"); return ERROR_TARGET_FAILURE; } - LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]); - - if (buffer[9] & 0x20) - armv4_5->core_state = ARMV4_5_STATE_THUMB; - else - armv4_5->core_state = ARMV4_5_STATE_ARM; - - - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) - return ERROR_FAIL; + LOG_DEBUG("target entered debug state in %s mode", + arm_mode_name(armv4_5->core_mode)); /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */ - if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS)) - { + if (armv4_5->spsr) { xscale_receive(target, buffer, 8); - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1; + buf_set_u32(armv4_5->spsr->value, 0, 32, buffer[7]); + armv4_5->spsr->dirty = false; + armv4_5->spsr->valid = true; } else { @@ -987,12 +985,14 @@ static int xscale_debug_entry(struct target *target) xscale_receive(target, buffer, 7); } - /* move data from buffer to register cache */ + /* move data from buffer to right banked register in cache */ for (i = 8; i <= 14; i++) { - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, buffer[i - 8]); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1; + struct reg *r = arm_reg_current(armv4_5, i); + + buf_set_u32(r->value, 0, 32, buffer[i - 8]); + r->dirty = false; + r->valid = true; } /* examine debug reason */ @@ -1192,7 +1192,7 @@ static int xscale_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { struct xscale_common *xscale = target_to_xscale(target); - struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + struct arm *armv4_5 = &xscale->armv4_5_common; struct breakpoint *breakpoint = target->breakpoints; uint32_t current_pc; int retval; @@ -1251,7 +1251,7 @@ static int xscale_resume(struct target *target, int current, xscale_enable_single_step(target, next_pc); /* restore banked registers */ - xscale_restore_context(target); + retval = xscale_restore_banked(target); /* send resume request (command 0x30 or 0x31) * clean the trace buffer if it is to be enabled (0x62) */ @@ -1264,8 +1264,10 @@ static int xscale_resume(struct target *target, int current, xscale_send_u32(target, 0x30); /* send CPSR */ - xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + xscale_send_u32(target, + buf_get_u32(armv4_5->cpsr->value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, + buf_get_u32(armv4_5->cpsr->value, 0, 32)); for (i = 7; i >= 0; i--) { @@ -1294,7 +1296,7 @@ static int xscale_resume(struct target *target, int current, xscale_enable_watchpoints(target); /* restore banked registers */ - xscale_restore_context(target); + retval = xscale_restore_banked(target); /* send resume request (command 0x30 or 0x31) * clean the trace buffer if it is to be enabled (0x62) */ @@ -1307,8 +1309,9 @@ static int xscale_resume(struct target *target, int current, xscale_send_u32(target, 0x30); /* send CPSR */ - xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); - LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + xscale_send_u32(target, buf_get_u32(armv4_5->cpsr->value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, + buf_get_u32(armv4_5->cpsr->value, 0, 32)); for (i = 7; i >= 0; i--) { @@ -1326,7 +1329,7 @@ static int xscale_resume(struct target *target, int current, if (!debug_execution) { /* registers are now invalid */ - armv4_5_invalidate_core_regs(target); + register_cache_invalidate(armv4_5->core_cache); target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); } @@ -1345,7 +1348,7 @@ static int xscale_step_inner(struct target *target, int current, uint32_t address, int handle_breakpoints) { struct xscale_common *xscale = target_to_xscale(target); - struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + struct arm *armv4_5 = &xscale->armv4_5_common; uint32_t next_pc; int retval; int i; @@ -1368,7 +1371,7 @@ static int xscale_step_inner(struct target *target, int current, return retval; /* restore banked registers */ - if ((retval = xscale_restore_context(target)) != ERROR_OK) + if ((retval = xscale_restore_banked(target)) != ERROR_OK) return retval; /* send resume request (command 0x30 or 0x31) @@ -1385,9 +1388,12 @@ static int xscale_step_inner(struct target *target, int current, return retval; /* send CPSR */ - if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK) + retval = xscale_send_u32(target, + buf_get_u32(armv4_5->cpsr->value, 0, 32)); + if (retval != ERROR_OK) return retval; - LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, + buf_get_u32(armv4_5->cpsr->value, 0, 32)); for (i = 7; i >= 0; i--) { @@ -1405,8 +1411,7 @@ static int xscale_step_inner(struct target *target, int current, target_call_event_callbacks(target, TARGET_EVENT_RESUMED); /* registers are now invalid */ - if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK) - return retval; + register_cache_invalidate(armv4_5->core_cache); /* wait for and process debug entry */ if ((retval = xscale_debug_entry(target)) != ERROR_OK) @@ -1424,7 +1429,7 @@ static int xscale_step_inner(struct target *target, int current, static int xscale_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); struct breakpoint *breakpoint = target->breakpoints; uint32_t current_pc; @@ -1487,7 +1492,8 @@ static int xscale_assert_reset(struct target *target) * end up in T-L-R, which would reset JTAG */ jtag_set_end_state(TAP_IDLE); - xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR); + xscale_jtag_set_instr(target->tap, + XSCALE_SELDCSR << xscale->xscale_variant); /* set Hold reset, Halt mode and Trap Reset */ buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1); @@ -1542,7 +1548,7 @@ static int xscale_deassert_reset(struct target *target) breakpoint = breakpoint->next; } - armv4_5_invalidate_core_regs(target); + register_cache_invalidate(xscale->armv4_5_common.core_cache); /* FIXME mark hardware watchpoints got unset too. Also, * at least some of the XScale registers are invalid... @@ -1651,23 +1657,25 @@ static int xscale_deassert_reset(struct target *target) return ERROR_OK; } -static int xscale_read_core_reg(struct target *target, int num, - enum armv4_5_mode mode) +static int xscale_read_core_reg(struct target *target, struct reg *r, + int num, enum armv4_5_mode mode) { + /** \todo add debug handler support for core register reads */ LOG_ERROR("not implemented"); return ERROR_OK; } -static int xscale_write_core_reg(struct target *target, int num, - enum armv4_5_mode mode, uint32_t value) +static int xscale_write_core_reg(struct target *target, struct reg *r, + int num, enum armv4_5_mode mode, uint32_t value) { + /** \todo add debug handler support for core register writes */ LOG_ERROR("not implemented"); return ERROR_OK; } static int xscale_full_context(struct target *target) { - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); uint32_t *buffer; @@ -1689,50 +1697,56 @@ static int xscale_full_context(struct target *target) */ for (i = 1; i < 7; i++) { - int valid = 1; + enum armv4_5_mode mode = armv4_5_number_to_mode(i); + bool valid = true; + struct reg *r; + + if (mode == ARMV4_5_MODE_USR) + continue; /* check if there are invalid registers in the current mode */ - for (j = 0; j <= 16; j++) + for (j = 0; valid && j <= 16; j++) { - if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0) - valid = 0; + if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + mode, j).valid) + valid = false; } + if (valid) + continue; - if (!valid) - { - uint32_t tmp_cpsr; - - /* request banked registers */ - xscale_send_u32(target, 0x0); + /* request banked registers */ + xscale_send_u32(target, 0x0); - tmp_cpsr = 0x0; - tmp_cpsr |= armv4_5_number_to_mode(i); - tmp_cpsr |= 0xc0; /* I/F bits */ + /* send CPSR for desired bank mode */ + xscale_send_u32(target, mode | 0xc0 /* I/F bits */); - /* send CPSR for desired mode */ - xscale_send_u32(target, tmp_cpsr); + /* get banked registers: r8 to r14; and SPSR + * except in USR/SYS mode + */ + if (mode != ARMV4_5_MODE_SYS) { + /* SPSR */ + r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + mode, 16); + + xscale_receive(target, buffer, 8); + + buf_set_u32(r->value, 0, 32, buffer[7]); + r->dirty = false; + r->valid = true; + } else { + xscale_receive(target, buffer, 7); + } - /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */ - if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS)) - { - xscale_receive(target, buffer, 8); - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1; - } - else - { - xscale_receive(target, buffer, 7); - } + /* move data from buffer to register cache */ + for (j = 8; j <= 14; j++) + { + r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + mode, j); - /* move data from buffer to register cache */ - for (j = 8; j <= 14; j++) - { - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value, 0, 32, buffer[j - 8]); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1; - } + buf_set_u32(r->value, 0, 32, buffer[j - 8]); + r->dirty = false; + r->valid = true; } } @@ -1741,9 +1755,9 @@ static int xscale_full_context(struct target *target) return ERROR_OK; } -static int xscale_restore_context(struct target *target) +static int xscale_restore_banked(struct target *target) { - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); int i, j; @@ -1754,54 +1768,60 @@ static int xscale_restore_context(struct target *target) } /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS) - * we can't enter User mode on an XScale (unpredictable), - * but User shares registers with SYS - */ + * and check if any banked registers need to be written. Ignore + * USR mode (number 0) in favor of SYS; we can't enter User mode on + * an XScale (unpredictable), but they share all registers. + */ for (i = 1; i < 7; i++) { - int dirty = 0; + enum armv4_5_mode mode = armv4_5_number_to_mode(i); + struct reg *r; - /* check if there are invalid registers in the current mode - */ + if (mode == ARMV4_5_MODE_USR) + continue; + + /* check if there are dirty registers in this mode */ for (j = 8; j <= 14; j++) { - if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty == 1) - dirty = 1; + if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + mode, j).dirty) + goto dirty; } /* if not USR/SYS, check if the SPSR needs to be written */ - if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS)) + if (mode != ARMV4_5_MODE_SYS) { - if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty == 1) - dirty = 1; + if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + mode, 16).dirty) + goto dirty; } - if (dirty) - { - uint32_t tmp_cpsr; - - /* send banked registers */ - xscale_send_u32(target, 0x1); + /* there's nothing to flush for this mode */ + continue; - tmp_cpsr = 0x0; - tmp_cpsr |= armv4_5_number_to_mode(i); - tmp_cpsr |= 0xc0; /* I/F bits */ +dirty: + /* command 0x1: "send banked registers" */ + xscale_send_u32(target, 0x1); - /* send CPSR for desired mode */ - xscale_send_u32(target, tmp_cpsr); + /* send CPSR for desired mode */ + xscale_send_u32(target, mode | 0xc0 /* I/F bits */); - /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */ - for (j = 8; j <= 14; j++) - { - xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, j).value, 0, 32)); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0; - } + /* send r8 to r14/lr ... only FIQ needs more than r13..r14, + * but this protocol doesn't understand that nuance. + */ + for (j = 8; j <= 14; j++) { + r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + mode, j); + xscale_send_u32(target, buf_get_u32(r->value, 0, 32)); + r->dirty = false; + } - if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS)) - { - xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32)); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0; - } + /* send spsr if not in USR/SYS mode */ + if (mode != ARMV4_5_MODE_SYS) { + r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + mode, 16); + xscale_send_u32(target, buf_get_u32(r->value, 0, 32)); + r->dirty = false; } } @@ -1887,6 +1907,15 @@ static int xscale_read_memory(struct target *target, uint32_t address, return ERROR_OK; } +static int xscale_read_phys_memory(struct target *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) +{ + /** \todo: provide a non-stub implementtion of this routine. */ + LOG_ERROR("%s: %s is not implemented. Disable MMU?", + target_name(target), __func__); + return ERROR_FAIL; +} + static int xscale_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { @@ -1965,6 +1994,15 @@ static int xscale_write_memory(struct target *target, uint32_t address, return ERROR_OK; } +static int xscale_write_phys_memory(struct target *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) +{ + /** \todo: provide a non-stub implementtion of this routine. */ + LOG_ERROR("%s: %s is not implemented. Disable MMU?", + target_name(target), __func__); + return ERROR_FAIL; +} + static int xscale_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer) { @@ -2125,12 +2163,6 @@ static int xscale_add_breakpoint(struct target *target, { struct xscale_common *xscale = target_to_xscale(target); - if (target->state != TARGET_HALTED) - { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1)) { LOG_INFO("no breakpoint unit available for hardware breakpoint"); @@ -2288,12 +2320,6 @@ static int xscale_add_watchpoint(struct target *target, { struct xscale_common *xscale = target_to_xscale(target); - if (target->state != TARGET_HALTED) - { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - if (xscale->dbr_available < 1) { return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; @@ -2476,7 +2502,7 @@ static int xscale_write_dcsr_sw(struct target *target, uint32_t value) static int xscale_read_trace(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); - struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + struct arm *armv4_5 = &xscale->armv4_5_common; struct xscale_trace_data **trace_data_p; /* 258 words from debug handler @@ -2819,21 +2845,21 @@ static int xscale_analyze_trace(struct target *target, struct command_context *c return ERROR_OK; } +static const struct reg_arch_type xscale_reg_type = { + .get = xscale_get_reg, + .set = xscale_set_reg, +}; + static void xscale_build_reg_cache(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); - struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + struct arm *armv4_5 = &xscale->armv4_5_common; struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info)); int i; - int num_regs = sizeof(xscale_reg_arch_info) / sizeof(struct xscale_reg); + int num_regs = ARRAY_SIZE(xscale_reg_arch_info); (*cache_p) = armv4_5_build_reg_cache(target, armv4_5); - armv4_5->core_cache = (*cache_p); - - /* register a register arch-type for XScale dbg registers only once */ - if (xscale_reg_arch_type == -1) - xscale_reg_arch_type = register_reg_arch_type(xscale_get_reg, xscale_set_reg); (*cache_p)->next = malloc(sizeof(struct reg_cache)); cache_p = &(*cache_p)->next; @@ -2852,7 +2878,7 @@ static void xscale_build_reg_cache(struct target *target) (*cache_p)->reg_list[i].valid = 0; (*cache_p)->reg_list[i].size = 32; (*cache_p)->reg_list[i].arch_info = &arch_info[i]; - (*cache_p)->reg_list[i].arch_type = xscale_reg_arch_type; + (*cache_p)->reg_list[i].type = &xscale_reg_type; arch_info[i] = xscale_reg_arch_info[i]; arch_info[i].target = target; } @@ -2876,10 +2902,10 @@ static int xscale_init_arch_info(struct target *target, armv4_5 = &xscale->armv4_5_common; - /* store architecture specfic data (none so far) */ + /* store architecture specfic data */ xscale->common_magic = XSCALE_COMMON_MAGIC; - /* we don't really *need* variant info ... */ + /* we don't really *need* a variant param ... */ if (variant) { int ir_length = 0; @@ -2892,6 +2918,8 @@ static int xscale_init_arch_info(struct target *target, || strcmp(variant, "ixp45x") == 0 || strcmp(variant, "ixp46x") == 0) ir_length = 7; + else if (strcmp(variant, "pxa3xx") == 0) + ir_length = 11; else LOG_WARNING("%s: unrecognized variant %s", tap->dotted_name, variant); @@ -2903,6 +2931,12 @@ static int xscale_init_arch_info(struct target *target, } } + /* PXA3xx shifts the JTAG instructions */ + if (tap->ir_length == 11) + xscale->xscale_variant = XSCALE_PXA3XX; + else + xscale->xscale_variant = XSCALE_IXP4XX_PXA2XX; + /* the debug handler isn't installed (and thus not running) at this time */ xscale->handler_address = 0xfe000800; @@ -2996,24 +3030,24 @@ COMMAND_HANDLER(xscale_handle_debug_handler_command) int retval; uint32_t handler_address; - if (argc < 2) + if (CMD_ARGC < 2) { LOG_ERROR("'xscale debug_handler
' command takes two required operands"); return ERROR_OK; } - if ((target = get_target(args[0])) == NULL) + if ((target = get_target(CMD_ARGV[0])) == NULL) { - LOG_ERROR("target '%s' not defined", args[0]); + LOG_ERROR("target '%s' not defined", CMD_ARGV[0]); return ERROR_FAIL; } xscale = target_to_xscale(target); - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; - COMMAND_PARSE_NUMBER(u32, args[1], handler_address); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], handler_address); if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) || ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800))) @@ -3036,23 +3070,23 @@ COMMAND_HANDLER(xscale_handle_cache_clean_address_command) int retval; uint32_t cache_clean_address; - if (argc < 2) + if (CMD_ARGC < 2) { return ERROR_COMMAND_SYNTAX_ERROR; } - target = get_target(args[0]); + target = get_target(CMD_ARGV[0]); if (target == NULL) { - LOG_ERROR("target '%s' not defined", args[0]); + LOG_ERROR("target '%s' not defined", CMD_ARGV[0]); return ERROR_FAIL; } xscale = target_to_xscale(target); - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; - COMMAND_PARSE_NUMBER(u32, args[1], cache_clean_address); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cache_clean_address); if (cache_clean_address & 0xffff) { @@ -3068,15 +3102,15 @@ COMMAND_HANDLER(xscale_handle_cache_clean_address_command) COMMAND_HANDLER(xscale_handle_cache_info_command) { - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; - return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache); + return armv4_5_handle_cache_info_command(CMD_CTX, &xscale->armv4_5_mmu.armv4_5_cache); } static int xscale_virt2phys(struct target *target, @@ -3117,114 +3151,99 @@ static int xscale_mmu(struct target *target, int *enabled) COMMAND_HANDLER(xscale_handle_mmu_command) { - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } - if (argc >= 1) + if (CMD_ARGC >= 1) { - if (strcmp("enable", args[0]) == 0) - { + bool enable; + COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable); + if (enable) xscale_enable_mmu_caches(target, 1, 0, 0); - xscale->armv4_5_mmu.mmu_enabled = 1; - } - else if (strcmp("disable", args[0]) == 0) - { + else xscale_disable_mmu_caches(target, 1, 0, 0); - xscale->armv4_5_mmu.mmu_enabled = 0; - } + xscale->armv4_5_mmu.mmu_enabled = enable; } - command_print(cmd_ctx, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled"); + command_print(CMD_CTX, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled"); return ERROR_OK; } COMMAND_HANDLER(xscale_handle_idcache_command) { - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); - int icache = 0, dcache = 0; - int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + int retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } - if (strcmp(CMD_NAME, "icache") == 0) - icache = 1; - else if (strcmp(CMD_NAME, "dcache") == 0) - dcache = 1; + bool icache; + COMMAND_PARSE_BOOL(CMD_NAME, icache, "icache", "dcache"); - if (argc >= 1) + if (CMD_ARGC >= 1) { - if (strcmp("enable", args[0]) == 0) - { - xscale_enable_mmu_caches(target, 0, dcache, icache); - - if (icache) - xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 1; - else if (dcache) - xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 1; - } - else if (strcmp("disable", args[0]) == 0) - { - xscale_disable_mmu_caches(target, 0, dcache, icache); - - if (icache) - xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; - else if (dcache) - xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; - } + bool enable; + COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable); + if (enable) + xscale_enable_mmu_caches(target, 1, 0, 0); + else + xscale_disable_mmu_caches(target, 1, 0, 0); + if (icache) + xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable; + else + xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable; } - if (icache) - command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled"); - - if (dcache) - command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled"); + bool enabled = icache ? + xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled : + xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled; + const char *msg = enabled ? "enabled" : "disabled"; + command_print(CMD_CTX, "%s %s", CMD_NAME, msg); return ERROR_OK; } COMMAND_HANDLER(xscale_handle_vector_catch_command) { - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; - if (argc < 1) + if (CMD_ARGC < 1) { - command_print(cmd_ctx, "usage: xscale vector_catch [mask]"); + command_print(CMD_CTX, "usage: xscale vector_catch [mask]"); } else { - COMMAND_PARSE_NUMBER(u8, args[0], xscale->vector_catch); + COMMAND_PARSE_NUMBER(u8, CMD_ARGV[0], xscale->vector_catch); buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch); xscale_write_dcsr(target, -1, -1); } - command_print(cmd_ctx, "vector catch mask: 0x%2.2x", xscale->vector_catch); + command_print(CMD_CTX, "vector catch mask: 0x%2.2x", xscale->vector_catch); return ERROR_OK; } @@ -3232,47 +3251,47 @@ COMMAND_HANDLER(xscale_handle_vector_catch_command) COMMAND_HANDLER(xscale_handle_vector_table_command) { - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); int err = 0; int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; - if (argc == 0) /* print current settings */ + if (CMD_ARGC == 0) /* print current settings */ { int idx; - command_print(cmd_ctx, "active user-set static vectors:"); + command_print(CMD_CTX, "active user-set static vectors:"); for (idx = 1; idx < 8; idx++) if (xscale->static_low_vectors_set & (1 << idx)) - command_print(cmd_ctx, "low %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]); + command_print(CMD_CTX, "low %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]); for (idx = 1; idx < 8; idx++) if (xscale->static_high_vectors_set & (1 << idx)) - command_print(cmd_ctx, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]); + command_print(CMD_CTX, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]); return ERROR_OK; } - if (argc != 3) + if (CMD_ARGC != 3) err = 1; else { int idx; - COMMAND_PARSE_NUMBER(int, args[1], idx); + COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], idx); uint32_t vec; - COMMAND_PARSE_NUMBER(u32, args[2], vec); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], vec); if (idx < 1 || idx >= 8) err = 1; - if (!err && strcmp(args[0], "low") == 0) + if (!err && strcmp(CMD_ARGV[0], "low") == 0) { xscale->static_low_vectors_set |= (1<static_low_vectors[idx] = vec; } - else if (!err && (strcmp(args[0], "high") == 0)) + else if (!err && (strcmp(CMD_ARGV[0], "high") == 0)) { xscale->static_high_vectors_set |= (1<static_high_vectors[idx] = vec; @@ -3282,7 +3301,7 @@ COMMAND_HANDLER(xscale_handle_vector_table_command) } if (err) - command_print(cmd_ctx, "usage: xscale vector_table "); + command_print(CMD_CTX, "usage: xscale vector_table "); return ERROR_OK; } @@ -3290,23 +3309,23 @@ COMMAND_HANDLER(xscale_handle_vector_table_command) COMMAND_HANDLER(xscale_handle_trace_buffer_command) { - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); - struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common; + struct arm *armv4_5 = &xscale->armv4_5_common; uint32_t dcsr_value; int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } - if ((argc >= 1) && (strcmp("enable", args[0]) == 0)) + if ((CMD_ARGC >= 1) && (strcmp("enable", CMD_ARGV[0]) == 0)) { struct xscale_trace_data *td, *next_td; xscale->trace.buffer_enabled = 1; @@ -3324,19 +3343,19 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command) } xscale->trace.data = NULL; } - else if ((argc >= 1) && (strcmp("disable", args[0]) == 0)) + else if ((CMD_ARGC >= 1) && (strcmp("disable", CMD_ARGV[0]) == 0)) { xscale->trace.buffer_enabled = 0; } - if ((argc >= 2) && (strcmp("fill", args[1]) == 0)) + if ((CMD_ARGC >= 2) && (strcmp("fill", CMD_ARGV[1]) == 0)) { uint32_t fill = 1; - if (argc >= 3) - COMMAND_PARSE_NUMBER(u32, args[2], fill); + if (CMD_ARGC >= 3) + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], fill); xscale->trace.buffer_fill = fill; } - else if ((argc >= 2) && (strcmp("wrap", args[1]) == 0)) + else if ((CMD_ARGC >= 2) && (strcmp("wrap", CMD_ARGV[1]) == 0)) { xscale->trace.buffer_fill = -1; } @@ -3354,7 +3373,7 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command) xscale->trace.pc_ok = 0; } - command_print(cmd_ctx, "trace buffer %s (%s)", + command_print(CMD_CTX, "trace buffer %s (%s)", (xscale->trace.buffer_enabled) ? "enabled" : "disabled", (xscale->trace.buffer_fill > 0) ? "fill" : "wrap"); @@ -3369,17 +3388,17 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command) COMMAND_HANDLER(xscale_handle_trace_image_command) { - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); int retval; - if (argc < 1) + if (CMD_ARGC < 1) { - command_print(cmd_ctx, "usage: xscale trace_image [base address] [type]"); + command_print(CMD_CTX, "usage: xscale trace_image [base address] [type]"); return ERROR_OK; } - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; @@ -3387,7 +3406,7 @@ COMMAND_HANDLER(xscale_handle_trace_image_command) { image_close(xscale->trace.image); free(xscale->trace.image); - command_print(cmd_ctx, "previously loaded image found and closed"); + command_print(CMD_CTX, "previously loaded image found and closed"); } xscale->trace.image = malloc(sizeof(struct image)); @@ -3395,17 +3414,17 @@ COMMAND_HANDLER(xscale_handle_trace_image_command) xscale->trace.image->start_address_set = 0; /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */ - if (argc >= 2) + if (CMD_ARGC >= 2) { xscale->trace.image->base_address_set = 1; - COMMAND_PARSE_NUMBER(int, args[1], xscale->trace.image->base_address); + COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], xscale->trace.image->base_address); } else { xscale->trace.image->base_address_set = 0; } - if (image_open(xscale->trace.image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK) + if (image_open(xscale->trace.image, CMD_ARGV[0], (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) { free(xscale->trace.image); xscale->trace.image = NULL; @@ -3417,25 +3436,25 @@ COMMAND_HANDLER(xscale_handle_trace_image_command) COMMAND_HANDLER(xscale_handle_dump_trace_command) { - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); struct xscale_trace_data *trace_data; struct fileio file; int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } - if (argc < 1) + if (CMD_ARGC < 1) { - command_print(cmd_ctx, "usage: xscale dump_trace "); + command_print(CMD_CTX, "usage: xscale dump_trace "); return ERROR_OK; } @@ -3443,11 +3462,11 @@ COMMAND_HANDLER(xscale_handle_dump_trace_command) if (!trace_data) { - command_print(cmd_ctx, "no trace data collected"); + command_print(CMD_CTX, "no trace data collected"); return ERROR_OK; } - if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK) + if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK) { return ERROR_OK; } @@ -3474,39 +3493,39 @@ COMMAND_HANDLER(xscale_handle_dump_trace_command) COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command) { - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; - xscale_analyze_trace(target, cmd_ctx); + xscale_analyze_trace(target, CMD_CTX); return ERROR_OK; } COMMAND_HANDLER(xscale_handle_cp15) { - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct xscale_common *xscale = target_to_xscale(target); int retval; - retval = xscale_verify_pointer(cmd_ctx, xscale); + retval = xscale_verify_pointer(CMD_CTX, xscale); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } uint32_t reg_no = 0; struct reg *reg = NULL; - if (argc > 0) + if (CMD_ARGC > 0) { - COMMAND_PARSE_NUMBER(u32, args[0], reg_no); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg_no); /*translate from xscale cp15 register no to openocd register*/ switch (reg_no) { @@ -3535,25 +3554,25 @@ COMMAND_HANDLER(xscale_handle_cp15) reg_no = XSCALE_CPACCESS; break; default: - command_print(cmd_ctx, "invalid register number"); + command_print(CMD_CTX, "invalid register number"); return ERROR_INVALID_ARGUMENTS; } reg = &xscale->reg_cache->reg_list[reg_no]; } - if (argc == 1) + if (CMD_ARGC == 1) { uint32_t value; /* read cp15 control register */ xscale_get_reg(reg); value = buf_get_u32(reg->value, 0, 32); - command_print(cmd_ctx, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size), value); + command_print(CMD_CTX, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size), value); } - else if (argc == 2) + else if (CMD_ARGC == 2) { uint32_t value; - COMMAND_PARSE_NUMBER(u32, args[1], value); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); /* send CP write request (command 0x41) */ xscale_send_u32(target, 0x41); @@ -3569,42 +3588,121 @@ COMMAND_HANDLER(xscale_handle_cp15) } else { - command_print(cmd_ctx, "usage: cp15 [register]<, [value]>"); + command_print(CMD_CTX, "usage: cp15 [register]<, [value]>"); } return ERROR_OK; } -static int xscale_register_commands(struct command_context *cmd_ctx) -{ - struct command *xscale_cmd; - - xscale_cmd = register_command(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands"); - - register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_ANY, "'xscale debug_handler
' command takes two required operands"); - register_command(cmd_ctx, xscale_cmd, "cache_clean_address", xscale_handle_cache_clean_address_command, COMMAND_ANY, NULL); - - register_command(cmd_ctx, xscale_cmd, "cache_info", xscale_handle_cache_info_command, COMMAND_EXEC, NULL); - register_command(cmd_ctx, xscale_cmd, "mmu", xscale_handle_mmu_command, COMMAND_EXEC, "['enable'|'disable'] the MMU"); - register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache"); - register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache"); - - register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, " of vectors that should be catched"); - register_command(cmd_ctx, xscale_cmd, "vector_table", xscale_handle_vector_table_command, COMMAND_EXEC, " set static code for exception handler entry"); - - register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, " ['fill' [n]|'wrap']"); - - register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to "); - register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer"); - register_command(cmd_ctx, xscale_cmd, "trace_image", xscale_handle_trace_image_command, - COMMAND_EXEC, "load image from [base address]"); - - register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 [value]"); - - armv4_5_register_commands(cmd_ctx); - - return ERROR_OK; -} +static const struct command_registration xscale_exec_command_handlers[] = { + { + .name = "cache_info", + .handler = &xscale_handle_cache_info_command, + .mode = COMMAND_EXEC, NULL, + }, + + { + .name = "mmu", + .handler = &xscale_handle_mmu_command, + .mode = COMMAND_EXEC, + .usage = "[enable|disable]", + .help = "enable or disable the MMU", + }, + { + .name = "icache", + .handler = &xscale_handle_idcache_command, + .mode = COMMAND_EXEC, + .usage = "[enable|disable]", + .help = "enable or disable the ICache", + }, + { + .name = "dcache", + .handler = &xscale_handle_idcache_command, + .mode = COMMAND_EXEC, + .usage = "[enable|disable]", + .help = "enable or disable the DCache", + }, + + { + .name = "vector_catch", + .handler = &xscale_handle_vector_catch_command, + .mode = COMMAND_EXEC, + .help = "mask of vectors that should be caught", + .usage = "[]", + }, + { + .name = "vector_table", + .handler = &xscale_handle_vector_table_command, + .mode = COMMAND_EXEC, + .usage = " ", + .help = "set static code for exception handler entry", + }, + + { + .name = "trace_buffer", + .handler = &xscale_handle_trace_buffer_command, + .mode = COMMAND_EXEC, + .usage = " [fill [n]|wrap]", + }, + { + .name = "dump_trace", + .handler = &xscale_handle_dump_trace_command, + .mode = COMMAND_EXEC, + .help = "dump content of trace buffer to ", + .usage = "", + }, + { + .name = "analyze_trace", + .handler = &xscale_handle_analyze_trace_buffer_command, + .mode = COMMAND_EXEC, + .help = "analyze content of trace buffer", + }, + { + .name = "trace_image", + .handler = &xscale_handle_trace_image_command, + COMMAND_EXEC, + .help = "load image from [base address]", + .usage = " [address] [type]", + }, + + { + .name = "cp15", + .handler = &xscale_handle_cp15, + .mode = COMMAND_EXEC, + .help = "access coproc 15", + .usage = " [value]", + }, + COMMAND_REGISTRATION_DONE +}; +static const struct command_registration xscale_any_command_handlers[] = { + { + .name = "debug_handler", + .handler = &xscale_handle_debug_handler_command, + .mode = COMMAND_ANY, + .usage = "
", + }, + { + .name = "cache_clean_address", + .handler = &xscale_handle_cache_clean_address_command, + .mode = COMMAND_ANY, + }, + { + .chain = xscale_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; +static const struct command_registration xscale_command_handlers[] = { + { + .chain = arm_command_handlers, + }, + { + .name = "xscale", + .mode = COMMAND_ANY, + .help = "xscale command group", + .chain = xscale_any_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; struct target_type xscale_target = { @@ -3626,7 +3724,9 @@ struct target_type xscale_target = .get_gdb_reg_list = armv4_5_get_gdb_reg_list, .read_memory = xscale_read_memory, + .read_phys_memory = xscale_read_phys_memory, .write_memory = xscale_write_memory, + .write_phys_memory = xscale_write_phys_memory, .bulk_write_memory = xscale_bulk_write_memory, .checksum_memory = arm_checksum_memory, @@ -3639,7 +3739,7 @@ struct target_type xscale_target = .add_watchpoint = xscale_add_watchpoint, .remove_watchpoint = xscale_remove_watchpoint, - .register_commands = xscale_register_commands, + .commands = xscale_command_handlers, .target_create = xscale_target_create, .init_target = xscale_init_target,