X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=src%2Ftarget%2Fxscale.h;h=e480da9307ffc0594195d90fcae3316388f52e2b;hb=8c6b95ed162ada54b1165ca0c9b46aa92f92975c;hp=9d92550a6c7b84a5a5bb1dd71de6900a6941c5c7;hpb=5e837387aa7260518cf43f53b66ee917d8660802;p=openocd.git

diff --git a/src/target/xscale.h b/src/target/xscale.h
index 9d92550a6c..e480da9307 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -23,7 +23,7 @@
 #ifndef XSCALE_H
 #define XSCALE_H
 
-#include "armv4_5.h"
+#include "arm.h"
 #include "armv4_5_mmu.h"
 #include "trace.h"
 
@@ -37,6 +37,10 @@
 #define XSCALE_LDIC	0x07
 #define XSCALE_SELDCSR	0x09
 
+/* Possible CPU types */
+#define	XSCALE_IXP4XX_PXA2XX	0x0
+#define	XSCALE_PXA3XX		0x4
+
 enum xscale_debug_reason
 {
 	XSCALE_DBG_REASON_GENERIC,
@@ -50,44 +54,51 @@ enum xscale_trace_entry_type
 	XSCALE_TRACE_ADDRESS = 0x1,
 };
 
-typedef struct xscale_trace_entry_s
+struct xscale_trace_entry
 {
 	uint8_t data;
 	enum xscale_trace_entry_type type;
-} xscale_trace_entry_t;
+};
 
-typedef struct xscale_trace_data_s
+struct xscale_trace_data
 {
-	xscale_trace_entry_t *entries;
+	struct xscale_trace_entry *entries;
 	int depth;
 	uint32_t chkpt0;
 	uint32_t chkpt1;
 	uint32_t last_instruction;
-	struct xscale_trace_data_s *next;
-} xscale_trace_data_t;
+	unsigned int num_checkpoints;
+	struct xscale_trace_data *next;
+};
+
+enum trace_mode
+{
+   XSCALE_TRACE_DISABLED,
+   XSCALE_TRACE_FILL,
+   XSCALE_TRACE_WRAP
+};
 
-typedef struct xscale_trace_s
+struct xscale_trace
 {
-	trace_status_t capture_status;	/* current state of capture run */
-	struct image_s *image;					/* source for target opcodes */
-	xscale_trace_data_t *data;		/* linked list of collected trace data */
-	int buffer_enabled;				/* whether trace buffer is enabled */
-	int buffer_fill;				/* maximum number of trace runs to read (-1 for wrap-around) */
-	int pc_ok;
-	uint32_t current_pc;
-	armv4_5_state_t core_state;		/* current core state (ARM, Thumb, Jazelle) */
-} xscale_trace_t;
-
-typedef struct xscale_common_s
+	struct image *image;					/* source for target opcodes */
+	struct xscale_trace_data *data;		/* linked list of collected trace data */
+	int buffer_fill;				/* maximum number of trace runs to read */
+    int fill_counter;				/* running count during trace collection */
+    enum trace_mode mode;
+	enum arm_state core_state;	/* current core state (ARM, Thumb) */
+};
+
+struct xscale_common
 {
+	/* armv4/5 common stuff */
+	struct arm armv4_5_common;
+
 	int common_magic;
 
 	/* XScale registers (CP15, DBG) */
-	reg_cache_t *reg_cache;
+	struct reg_cache *reg_cache;
 
 	/* current state of the debug handler */
-	int handler_installed;
-	int handler_running;
 	uint32_t handler_address;
 
 	/* target-endian buffers with exception vectors */
@@ -119,28 +130,32 @@ typedef struct xscale_common_s
 
 	uint8_t vector_catch;
 
-	xscale_trace_t trace;
+	struct xscale_trace trace;
 
 	int arch_debug_reason;
 
-	/* armv4/5 common stuff */
-	armv4_5_common_t armv4_5_common;
-
 	/* MMU/Caches */
-	armv4_5_mmu_common_t armv4_5_mmu;
+	struct armv4_5_mmu_common armv4_5_mmu;
 	uint32_t cp15_control_reg;
 
-	/* possible future enhancements that go beyond XScale common stuff */
-	void *arch_info;
-
 	int fast_memory_access;
-} xscale_common_t;
 
-typedef struct xscale_reg_s
+	/* CPU variant */
+	int xscale_variant;
+};
+
+static inline struct xscale_common *
+target_to_xscale(struct target *target)
+{
+	return container_of(target->arch_info, struct xscale_common,
+			armv4_5_common);
+}
+
+struct xscale_reg
 {
 	int dbg_handler_number;
-	target_t *target;
-} xscale_reg_t;
+	struct target *target;
+};
 
 enum
 {
@@ -168,12 +183,6 @@ enum
 	XSCALE_TXRXCTRL,
 };
 
-#define ERROR_XSCALE_NO_TRACE_DATA	(-1500)
-
-/* This XScale "debug handler" is loaded into the processor's
- * mini-ICache, which is 2K of code writable only via JTAG.
- */
-extern const uint8_t xscale_debug_handler[];
-extern const uint32_t xscale_debug_handler_size;
+#define ERROR_XSCALE_NO_TRACE_DATA	(-700)
 
 #endif /* XSCALE_H */