X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Fboard%2Feir.cfg;h=a014e116bfc4c825ac4d036e269869d30ec4ede8;hb=f1427cca3cc6097a4635b4095ad1e30c8a508ac0;hp=087656585d30f2107100c63c423d3714e7bf354e;hpb=dbbc9c41f7db210b0a4e226540a28e0a8a5019bf;p=openocd.git

diff --git a/tcl/board/eir.cfg b/tcl/board/eir.cfg
index 087656585d..a014e116bf 100644
--- a/tcl/board/eir.cfg
+++ b/tcl/board/eir.cfg
@@ -4,7 +4,7 @@
 source [find target/sam7se512.cfg]
 
 $_TARGETNAME configure -event reset-init {
-	# WDT_MR, disable watchdog 
+	# WDT_MR, disable watchdog
 	mww 0xFFFFFD44 0x00008000
 
 	# RSTC_MR, enable user reset
@@ -30,60 +30,60 @@ $_TARGETNAME configure -event reset-init {
 	#
 
 	# Enable SDRAM control at PIO A.
-	mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
-	mww 0xfffff404 0x3f800000 # PIO_PDR_OFF
+	mww 0xfffff474 0x3f800000 ;# PIO_BSR_OFF
+	mww 0xfffff404 0x3f800000 ;# PIO_PDR_OFF
 
 	# Enable address bus (A0, A2-A11, A13-A17) at PIO B
-	mww 0xfffff674 0x0003effd # PIO_BSR_OFF
-	mww 0xfffff604 0x0003effd # PIO_PDR_OFF
+	mww 0xfffff674 0x0003effd ;# PIO_BSR_OFF
+	mww 0xfffff604 0x0003effd ;# PIO_PDR_OFF
 
 	# Enable 16 bit data bus at PIO C
-	mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
-	mww 0xfffff804 0x0000ffff # PIO_PDR_OFF
+	mww 0xfffff870 0x0000ffff ;# PIO_ASR_OFF
+	mww 0xfffff804 0x0000ffff ;# PIO_PDR_OFF
 
 	# Enable SDRAM chip select
-	mww 0xffffff80 0x00000002 # EBI_CSA_OFF
+	mww 0xffffff80 0x00000002 ;# EBI_CSA_OFF
 
 	# Set SDRAM characteristics in configuration register.
 	# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
-	mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
+	mww 0xffffffb8 0x2192215a ;# SDRAMC_CR_OFF
 	sleep 10
 
 	# Issue 16 bit SDRAM command: NOP
-	mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0xffffffb0 0x00000011 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
 
 	# Issue 16 bit SDRAM command: Precharge all
-	mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0xffffffb0 0x00000012 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
 
 	# Issue 8 auto-refresh cycles
-	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
-
-	# Issue 16 bit SDRAM command: Set mode register  
-	mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+	mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
+	mww 0x20000000 0x00000000
+
+	# Issue 16 bit SDRAM command: Set mode register
+	mww 0xffffffb0 0x00000013 ;# SDRAMC_MR_OFF
 	mww 0x20000014 0xcafedede
 
 	# Set refresh rate count ???
-	mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF
+	mww 0xffffffb4 0x00000013 ;# SDRAMC_TR_OFF
 
 	# Issue 16 bit SDRAM command: Normal mode
-	mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
+	mww 0xffffffb0 0x00000010 ;# SDRAMC_MR_OFF
 	mww 0x20000000 0x00000180
 
 	#