X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Fboard%2Fmini2440.cfg;h=c5adac360fc6e37a899385b98cb54c7147218fa1;hb=29d2d15f3fe66d611bc5e9e7ad36af704491a1c1;hp=8497bddf424674b92cadabbc460598146da57b94;hpb=71af49ca7fb11b0bd0c1ba9578826f49288b68ef;p=openocd.git diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg index 8497bddf42..c5adac360f 100644 --- a/tcl/board/mini2440.cfg +++ b/tcl/board/mini2440.cfg @@ -71,6 +71,11 @@ # # # + +# FIXME use some standard target config, maybe create one from this +# +# source [find target/...cfg] + #------------------------------------------------------------------------- # Target configuration for the Samsung 2440 system on chip # Tested on a S3C2440 Evaluation board by keesj @@ -102,12 +107,12 @@ if { [info exists CPUTAPID ] } { #jtag scan chain jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID -set _TARGETNAME [format "%s.cpu" $_CHIPNAME] -target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm920t -$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 1 +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 1 #reset configuration -jtag_nsrst_delay 100 +adapter_nsrst_delay 100 jtag_ntrst_delay 100 reset_config trst_and_srst @@ -116,18 +121,14 @@ reset_config trst_and_srst # IMPORTANT! See README at top of this file. #------------------------------------------------------------------------- - jtag_khz 12000 + adapter_khz 12000 jtag interface #------------------------------------------------------------------------- # GDB Setup #------------------------------------------------------------------------- - gdb_port 3333 - gdb_detach resume gdb_breakpoint_override hard - gdb_memory_map enable - gdb_flash_program enable #------------------------------------------------ # ARM SPECIFIC @@ -140,7 +141,7 @@ reset_config trst_and_srst nand device s3c2440 0 - jtag_nsrst_delay 100 + adapter_nsrst_delay 100 jtag_ntrst_delay 100 reset_config trst_and_srst init @@ -181,10 +182,10 @@ proc init_2440 { } { # usb clock are off 12mHz xtal #----------------------------------------------- - arm920t mww_phys 0x4C000014 0x00000005 # Clock Divider control Reg - arm920t mww_phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register - arm920t mww_phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg - arm920t mww_phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg + mww phys 0x4C000014 0x00000005 ;# Clock Divider control Reg + mww phys 0x4C000000 0xFFFFFFFF ;# LOCKTIME count register + mww phys 0x4C000008 0x00038022 ;# UPPLCON USB clock config Reg + mww phys 0x4C000004 0x0007F021 ;# MPPLCON Proc clock config Reg #----------------------------------------------- # Configure Memory controller @@ -192,45 +193,45 @@ proc init_2440 { } { # DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7 #----------------------------------------------- - arm920t mww_phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width - arm920t mww_phys 0x48000010 0x00001112 # BANKCON4 - ? - arm920t mww_phys 0x4800001c 0x00018009 # BANKCON6 - DRAM - arm920t mww_phys 0x48000020 0x00018009 # BANKCON7 - DRAM - arm920t mww_phys 0x48000024 0x008E04EB # REFRESH - DRAM - arm920t mww_phys 0x48000028 0x000000B2 # BANKSIZE - DRAM - arm920t mww_phys 0x4800002C 0x00000030 # MRSRB6 - DRAM - arm920t mww_phys 0x48000030 0x00000030 # MRSRB7 - DRAM + mww phys 0x48000000 0x22111112 ;# BWSCON - Bank and Bus Width + mww phys 0x48000010 0x00001112 ;# BANKCON4 - ? + mww phys 0x4800001c 0x00018009 ;# BANKCON6 - DRAM + mww phys 0x48000020 0x00018009 ;# BANKCON7 - DRAM + mww phys 0x48000024 0x008E04EB ;# REFRESH - DRAM + mww phys 0x48000028 0x000000B2 ;# BANKSIZE - DRAM + mww phys 0x4800002C 0x00000030 ;# MRSRB6 - DRAM + mww phys 0x48000030 0x00000030 ;# MRSRB7 - DRAM #----------------------------------------------- # Now port configuration for enables for memory # and other stuff. #----------------------------------------------- - arm920t mww_phys 0x56000000 0x007FFFFF # GPACON + mww phys 0x56000000 0x007FFFFF ;# GPACON - arm920t mww_phys 0x56000010 0x00295559 # GPBCON - arm920t mww_phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE) - arm920t mww_phys 0x56000014 0x000007C2 # GPBDAT + mww phys 0x56000010 0x00295559 ;# GPBCON + mww phys 0x56000018 0x000003FF ;# GPBUP (PULLUP ENABLE) + mww phys 0x56000014 0x000007C2 ;# GPBDAT - arm920t mww_phys 0x56000020 0xAAAAA6AA # GPCCON - arm920t mww_phys 0x56000028 0x0000FFFF # GPCUP - arm920t mww_phys 0x56000024 0x00000020 # GPCDAT + mww phys 0x56000020 0xAAAAA6AA ;# GPCCON + mww phys 0x56000028 0x0000FFFF ;# GPCUP + mww phys 0x56000024 0x00000020 ;# GPCDAT - arm920t mww_phys 0x56000030 0xAAAAAAAA # GPDCON - arm920t mww_phys 0x56000038 0x0000FFFF # GPDUP + mww phys 0x56000030 0xAAAAAAAA ;# GPDCON + mww phys 0x56000038 0x0000FFFF ;# GPDUP - arm920t mww_phys 0x56000040 0xAAAAAAAA # GPECON - arm920t mww_phys 0x56000048 0x0000FFFF # GPEUP + mww phys 0x56000040 0xAAAAAAAA ;# GPECON + mww phys 0x56000048 0x0000FFFF ;# GPEUP - arm920t mww_phys 0x56000050 0x00001555 # GPFCON - arm920t mww_phys 0x56000058 0x0000007F # GPFUP - arm920t mww_phys 0x56000054 0x00000000 # GPFDAT + mww phys 0x56000050 0x00001555 ;# GPFCON + mww phys 0x56000058 0x0000007F ;# GPFUP + mww phys 0x56000054 0x00000000 ;# GPFDAT - arm920t mww_phys 0x56000060 0x00150114 # GPGCON - arm920t mww_phys 0x56000068 0x0000007F # GPGUP + mww phys 0x56000060 0x00150114 ;# GPGCON + mww phys 0x56000068 0x0000007F ;# GPGUP - arm920t mww_phys 0x56000070 0x0015AAAA # GPHCON - arm920t mww_phys 0x56000078 0x000003FF # GPGUP + mww phys 0x56000070 0x0015AAAA ;# GPHCON + mww phys 0x56000078 0x000003FF ;# GPGUP } @@ -296,7 +297,7 @@ proc load_uboot { } { proc s {} { step reg - armv4_5 disassemble 0x33F80068 0x10 + arm disassemble 0x33F80068 0x10 } proc help_2440 {} {