X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Famdm37x.cfg;h=7098adfa3482b7113cb0893fb7cde5455cb185be;hb=38ac08c1c25adf42cf20e48e10e6ddeab6a12d71;hp=59fbbf01cd7cd929151d56f9831648b625976172;hpb=8d86633eb7c4cc74c3bf4c19eafa49ae76743c7b;p=openocd.git

diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg
index 59fbbf01cd..7098adfa34 100644
--- a/tcl/target/amdm37x.cfg
+++ b/tcl/target/amdm37x.cfg
@@ -45,7 +45,7 @@ if { [info exists CHIPTYPE] } {
 
 # Run the adapter at the fastest acceptable speed with the slowest possible
 # core clock.
-adapter_khz 10
+adapter speed 10
 
 ###############################################################################
 # JTAG setup
@@ -86,8 +86,8 @@ source [find target/icepick.cfg]
 
 # Secondary TAP: DAP is closest to the TDO output
 # The TAP enable event also needs to be described
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable \
    "icepick_c_tapenable $_CHIPNAME.jrc 3"
 
 # These taps are only present in the DM37x series.
@@ -141,7 +141,8 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
 
 # Create the CPU target to be used with GDB:  Cortex-A8, using DAP
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
 
 # The DM37x has 64K of SRAM starting at address 0x4020_0000.  Allow the first
 # 16K to be used as a scratchpad for OpenOCD.
@@ -156,7 +157,7 @@ $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
 #  slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
 #  *after* PLL and clock tree setup.
 
-$_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
+$_TARGETNAME configure -event "reset-start" { adapter speed 10 }
 
 # Describe the reset assert process for openocd - this is asserted with the
 # ICEPick
@@ -175,7 +176,7 @@ $_TARGETNAME configure -event reset-assert-post {
 
    global _TARGETNAME
    amdm37x_dbginit $_TARGETNAME
-   adapter_khz 1000
+   adapter speed 1000
 }
 
 $_TARGETNAME configure -event gdb-attach {
@@ -199,7 +200,7 @@ $_TARGETNAME configure -event gdb-attach {
 # Run this to enable invasive debugging.  This is run automatically in the
 # reset sequence.
 proc amdm37x_dbginit {target} {
-   # General Cortex A8 debug initialisation
+   # General Cortex-A8 debug initialisation
    cortex_a dbginit
 
    # Enable DBGEN signal.  This signal is described in the ARM v7 TRM, but