X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fat91eb40a.cfg;h=064a3b56853d151f2b89d8450bda93fdc2a74c8d;hb=4a91b070ffd7890c5a0b6381997787136d797bd5;hp=39fbe095ae417fa0113d806d5eff70fda7665f76;hpb=dbbc9c41f7db210b0a4e226540a28e0a8a5019bf;p=openocd.git

diff --git a/tcl/target/at91eb40a.cfg b/tcl/target/at91eb40a.cfg
index 39fbe095ae..064a3b5685 100644
--- a/tcl/target/at91eb40a.cfg
+++ b/tcl/target/at91eb40a.cfg
@@ -1,14 +1,14 @@
 #Script for AT91EB40a
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME at91eb40a
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
    set  _ENDIAN little
 }
 
@@ -28,13 +28,13 @@ if { [info exists CPUTAPID ] } {
 #SRST reset, which means that the CPU will run a number
 #of cycles before it can be halted(as much as milliseconds).
 reset_config srst_only srst_pulls_trst
- 
+
 #jtag scan chain
 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 #target configuration
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
 
 # speed up memory downloads
@@ -53,9 +53,9 @@ $_TARGETNAME configure -event reset-init {
 	# Reset script for AT91EB40a
 	reg cpsr 0x000000D3
 	mww 0xFFE00020 0x1
-	mww 0xFFE00024 0x00000000  
-	mww 0xFFE00000 0x01002539 
-	mww 0xFFFFF124 0xFFFFFFFF  
+	mww 0xFFE00024 0x00000000
+	mww 0xFFE00000 0x01002539
+	mww 0xFFFFF124 0xFFFFFFFF
 	mww 0xffff0010 0x100
 	mww 0xffff0034 0x100
 }