X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fdavinci.cfg;h=859a92539a0a0faef1854cbef78d8e89c56b444a;hb=45b4998e9369029d48c1f33fbccb1a525793cd46;hp=11ae093f56cf779e5e73603795b60f64b7d1903d;hpb=4ed89e4e42e1f2f62fdf6d0c660b2ea64479d136;p=openocd.git diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg index 11ae093f56..859a92539a 100644 --- a/tcl/target/davinci.cfg +++ b/tcl/target/davinci.cfg @@ -2,25 +2,12 @@ # Utility code for DaVinci-family chips # -# davinci_pinmux: assigns PINMUX$reg <== $value +# davinci_pinmux: assigns PINMUX$reg <== $value proc davinci_pinmux {soc reg value} { mww [expr [dict get $soc sysbase] + 4 * $reg] $value } -# mrw: "memory read word", returns value of $reg -proc mrw {reg} { - set value "" - mem2array value 32 $reg 1 - return $value(0) -} - -# mmw: "memory modify word", updates value of $reg -# $reg <== ((value & ~$clearbits) | $setbits) -proc mmw {reg setbits clearbits} { - set old [mrw $reg] - set new [expr ($old & ~$clearbits) | $setbits] - mww $reg $new -} +source [find mem_helper.tcl] # # pll_setup: initialize PLL @@ -33,13 +20,13 @@ proc mmw {reg setbits clearbits} { # # PLL version 0x02: tested on dm355 -# REVISIT: On dm6446/dm357 the PLLRST polarity is different. +# REVISIT: On dm6446/dm357 the PLLRST polarity is different. proc pll_v02_setup {pll_addr mult config} { set pll_ctrl_addr [expr $pll_addr + 0x100] set pll_ctrl [mrw $pll_ctrl_addr] # 1 - clear CLKMODE (bit 8) iff using on-chip oscillator - # NOTE: this assumes we should clear that bit + # NOTE: this assumes we should clear that bit set pll_ctrl [expr $pll_ctrl & ~0x0100] mww $pll_ctrl_addr $pll_ctrl @@ -70,8 +57,8 @@ proc pll_v02_setup {pll_addr mult config} { set pll_ctrl [expr $pll_ctrl & ~0x0010] mww $pll_ctrl_addr $pll_ctrl - # 9 - optional: write prediv, postdiv, and pllm - # NOTE: for dm355 PLL1, postdiv is controlled via MISC register + # 9 - optional: write prediv, postdiv, and pllm + # NOTE: for dm355 PLL1, postdiv is controlled via MISC register mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff] if { [dict exists $config prediv] } { set div [dict get $config prediv] @@ -84,7 +71,7 @@ proc pll_v02_setup {pll_addr mult config} { mww [expr $pll_addr + 0x0128] $div } - # 10 - optional: set plldiv1, plldiv2, ... + # 10 - optional: set plldiv1, plldiv2, ... # NOTE: this assumes some registers have their just-reset values: # - PLLSTAT.GOSTAT is clear when we enter # - ALNCTL has everything set @@ -175,7 +162,7 @@ proc pll_v03_setup {pll_addr mult config} { set pll_ctrl [expr $pll_ctrl & ~0x0008] mww $pll_ctrl_addr $pll_ctrl - # 9 - optional: write prediv, postdiv, and pllm + # 9 - optional: write prediv, postdiv, and pllm mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff] if { [dict exists $config prediv] } { set div [dict get $config prediv] @@ -194,8 +181,8 @@ proc pll_v03_setup {pll_addr mult config} { mww $pll_secctrl_addr 0x00400000 mww $pll_secctrl_addr 0x00410000 - # 11 - optional: set plldiv1, plldiv2, ... - # NOTE: this assumes some registers have their just-reset values: + # 11 - optional: set plldiv1, plldiv2, ... + # NOTE: this assumes some registers have their just-reset values: # - PLLSTAT.GOSTAT is clear when we enter set aln 0 if { [dict exists $config div1] } { @@ -222,6 +209,13 @@ proc pll_v03_setup {pll_addr mult config} { } else { mww [expr $pll_addr + 0x0120] 0 } + if { [dict exists $config oscdiv] } { + set div [dict get $config oscdiv] + set div [expr 0x8000 | ($div - 1)] + mww [expr $pll_addr + 0x0124] $div + } else { + mww [expr $pll_addr + 0x0124] 0 + } if { [dict exists $config div4] } { set div [dict get $config div4] set div [expr 0x8000 | ($div - 1)] @@ -289,7 +283,7 @@ proc pll_v03_setup {pll_addr mult config} { mww $pll_ctrl_addr $pll_ctrl } -# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain +# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain # modules can be enabled. # prepare a non-DSP module to be enabled; finish with psc_go