X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fimx31.cfg;h=ca639515f1badc6d60e1301772a7302af5487503;hb=76a765adbc8d6e20ed8adcd4839132017304e7d6;hp=fa7e2d21f31d21747c5ea0fde865f2d46da932d8;hpb=ce89c7bf6588c7b2800c4ca453278b6f94795130;p=openocd.git diff --git a/tcl/target/imx31.cfg b/tcl/target/imx31.cfg index fa7e2d21f3..ca639515f1 100644 --- a/tcl/target/imx31.cfg +++ b/tcl/target/imx31.cfg @@ -1,49 +1,51 @@ # imx31 config # -reset_config trst_and_srst +reset_config trst_and_srst srst_gates_jtag -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME imx31 +adapter_nsrst_delay 5 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx31 } -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little } -if { [info exists CPUTAPID ] } { +if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { set _CPUTAPID 0x07b3601d } -if { [info exists SDMATAPID ] } { +if { [info exists SDMATAPID] } { set _SDMATAPID $SDMATAPID } else { set _SDMATAPID 0x2190101d } -#======================================== -# The "system jtag controller" -# IMX31 reference manual, page 6-28 - figure 6-14 -if { [info exists SJCTAPID ] } { - set _SJCTAPID $SJCTAPID +if { [info exists ETBTAPID] } { + set _ETBTAPID $ETBTAPID } else { - set _SJCTAPID 0x2b900f0f + set _ETBTAPID 0x2b900f0f } -jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id $_SJCTAPID + +#======================================== + +jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID # The "SDMA" - mart controller debug tap # Based on some IO pins - this can be disabled & removed # See diagram: 6-14 # SIGNAL NAME: # SJC_MOD - controls multiplexer - disables ARM1136 -# SDMA_BYPASS - disables SDMA - -# +# SDMA_BYPASS - disables SDMA - +# # Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID @@ -58,5 +60,9 @@ set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME -proc power_restore {} { puts "Sensed power restore. No action." } -proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." } +proc power_restore {} { echo "Sensed power restore. No action." } +proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." } + +# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode +etm config $_TARGETNAME 16 normal full etb +etb config $_TARGETNAME $_CHIPNAME.etb