X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fimx6.cfg;h=5b59ecf86a7111de8135da4f3753dc79b438eff2;hb=1f37b94859e01c565219a7e7d6ddd85d122f7892;hp=afdf9614a5579a60236cd03f3e9fe428b9a3f67d;hpb=6018406c78d19d19f875973f598929546aaa3608;p=openocd.git

diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg
index afdf9614a5..5b59ecf86a 100644
--- a/tcl/target/imx6.cfg
+++ b/tcl/target/imx6.cfg
@@ -13,7 +13,7 @@ if { [info exists DAP_TAPID] } {
         set _DAP_TAPID 0x4ba00477
 }
 
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
         -expected-id $_DAP_TAPID
 
 # SDMA / no IDCODE
@@ -27,10 +27,11 @@ if { [info exists SJC_TAPID] } {
 }
 set _SJC_TAPID2 0x2191c01d
 set _SJC_TAPID3 0x2191e01d
+set _SJC_TAPID4 0x1191c01d
 
 jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
         -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \
-        -expected-id $_SJC_TAPID3
+        -expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4
 
 # GDB target: Cortex-A9, using DAP, configuring only one core
 # Base addresses of cores:
@@ -39,14 +40,15 @@ jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
 # core 2  -  0x82154000
 # core 3  -  0x82156000
 set _TARGETNAME $_CHIPNAME.cpu.0
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
         -coreid 0 -dbgbase 0x82150000
 
 # some TCK cycles are required to activate the DEBUG power domain
 jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
 
 proc imx6_dbginit {target} {
-        # General Cortex A8/A9 debug initialisation
+        # General Cortex-A8/A9 debug initialisation
         cortex_a dbginit
 }