X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Flpc1767.cfg;fp=tcl%2Ftarget%2Flpc1767.cfg;h=825dbebc679b7ce40708dfc63fb4317d9d0e9552;hb=ee8df96b2b064fd666e9a3aa8b8f03eb0f2bd75f;hp=0000000000000000000000000000000000000000;hpb=8fe2bed92c993242038c60273d1bb73f572e795e;p=openocd.git

diff --git a/tcl/target/lpc1767.cfg b/tcl/target/lpc1767.cfg
new file mode 100644
index 0000000000..825dbebc67
--- /dev/null
+++ b/tcl/target/lpc1767.cfg
@@ -0,0 +1,21 @@
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1767 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
+set CHIPNAME lpc1767
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x80000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];