X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Flpc1768.cfg;h=2059aedd866440b60e50532cfebb6f3440b4c901;hb=e7d26173fcd41640a85b9e315868768d7f297cda;hp=07c5ab8377d5889d7337585d79d9c69f26bba3ee;hpb=f60a2390cc5abe3d01633d9793ac1791fd0a3a5d;p=openocd.git diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg index 07c5ab8377..2059aedd86 100644 --- a/tcl/target/lpc1768.cfg +++ b/tcl/target/lpc1768.cfg @@ -1,5 +1,9 @@ # NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +# LPC17xx chips support both JTAG and SWD transports. +# Adapt based on what transport is active. +source [find target/swj-dp.tcl] + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { @@ -28,10 +32,8 @@ if { [info exists CPUTAPID ] } { adapter_nsrst_delay 200 jtag_ntrst_delay 200 -# LPC2000 & LPC1700 -> SRST causes TRST -reset_config srst_pulls_trst - -jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME @@ -47,18 +49,10 @@ set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \ lpc1700 $_CCLK calc_checksum -# Although rclk "appears to work", it turns out that this yields -# 4MHz whereas the "correct" rate is CCLK/6, which is not what -# you get with rclk. -# -# Also, crank down the frequency further as we're running of an -# RC oscillator instead of crystal. -# -# Setting up XTAL in the reset-init sequence could be worth -# the effort if you need to program the flash which is pretty -# big on these devices. -# -jtag_khz 100 +# Run with *real slow* clock by default since the +# boot rom could have been playing with the PLL, so +# we have no idea what clock the target is running at. +jtag_khz 10 $_TARGETNAME configure -event reset-init { # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select