X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Flpc1768.cfg;h=a436b30f69bbdee7b6bbb7257d909790eb0ece51;hb=f91390f538f22678a790f77320ec78cce76b0ebb;hp=07c5ab8377d5889d7337585d79d9c69f26bba3ee;hpb=f60a2390cc5abe3d01633d9793ac1791fd0a3a5d;p=openocd.git

diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg
index 07c5ab8377..a436b30f69 100644
--- a/tcl/target/lpc1768.cfg
+++ b/tcl/target/lpc1768.cfg
@@ -1,10 +1,8 @@
 # NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
-
-if { [info exists CHIPNAME] } {
-	set  _CHIPNAME $CHIPNAME
-} else {
-	set  _CHIPNAME lpc1768
-}
+set CHIPNAME lpc1768
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x80000
 
 # After reset the chip is clocked by the ~4MHz internal RC oscillator.
 # When board-specific code (reset-init handler or device firmware)
@@ -13,67 +11,7 @@ if { [info exists CHIPNAME] } {
 # (The ROM code doing those updates cares about core clock speed...)
 #
 # CCLK is the core clock frequency in KHz
-if { [info exists CCLK ] } {
-	set _CCLK $CCLK
-} else {
-	set _CCLK 4000
-}
-if { [info exists CPUTAPID ] } {
-	set _CPUTAPID $CPUTAPID
-} else {
-	set _CPUTAPID 0x4ba00477
-}
-
-#delays on reset lines
-adapter_nsrst_delay 200
-jtag_ntrst_delay 200
-
-# LPC2000 & LPC1700 -> SRST causes TRST
-reset_config srst_pulls_trst
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
-
-# LPC1768 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
-# and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
-$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
-
-# LPC1768 has 512kB of flash memory, managed by ROM code (including a
-# boot loader which verifies the flash exception table's checksum).
-# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \
-	lpc1700 $_CCLK calc_checksum
-
-# Although rclk "appears to work", it turns out that this yields
-# 4MHz whereas the "correct" rate is CCLK/6, which is not what
-# you get with rclk.
-#
-# Also, crank down the frequency further as we're running of an
-# RC oscillator instead of crystal.
-#
-# Setting up XTAL in the reset-init sequence could be worth 
-# the effort if you need to program the flash which is pretty
-# big on these devices.
-#
-jtag_khz 100
-
-$_TARGETNAME configure -event reset-init {
-	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
-	# "User Flash Mode" where interrupt vectors are _not_ remapped,
-	# and reside in flash instead).
-	#
-	# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
-	# Bit Symbol Value Description Reset
-	# value
-	# 0 MAP Memory map control. 0
-	# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
-	# 1 User mode. The on-chip Flash memory is mapped to address 0.
-	# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
-	#
-	# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
+set CCLK 4000
 
-	mww 0x400FC040 0x01
-}
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];