X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Flpc4350.cfg;h=2b728840ebe31417eff35d306efad04a42dfb5ed;hb=98a07154bc588d40b16f4f07b70937133f55e97e;hp=6614383b89dff72a0e71f3f1ee2e1d9c9f075dcb;hpb=2ce4e31bbcfabc06b7ac71d2e507e707d293c5c0;p=openocd.git

diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg
index 6614383b89..2b728840eb 100644
--- a/tcl/target/lpc4350.cfg
+++ b/tcl/target/lpc4350.cfg
@@ -1,3 +1,4 @@
+source [find target/swj-dp.tcl]
 
 adapter_khz 500
 
@@ -25,6 +26,12 @@ if { [info exists M4_SWD_TAPID] } {
 	set _M4_SWD_TAPID 0x2ba01477
 }
 
+if { [using_jtag] } {
+	set _M4_TAPID $_M4_JTAG_TAPID
+} {
+	set _M4_TAPID $_M4_SWD_TAPID
+}
+
 #
 # M0 TAP
 #
@@ -34,15 +41,32 @@ if { [info exists M0_JTAG_TAPID] } {
 	set _M0_JTAG_TAPID 0x0ba01477
 }
 
-jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
-				-expected-id $_M4_JTAG_TAPID
+swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
+				-expected-id $_M4_TAPID
+dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
+target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
 
-jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
+if { [using_jtag] } {
+	swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
 				-expected-id $_M0_JTAG_TAPID
+	dap create $_CHIPNAME.m0.dap -chain-position $_CHIPNAME.m0
+	target create $_CHIPNAME.m0 cortex_m -dap $_CHIPNAME.m0.dap
+}
 
-target create $_CHIPNAME.m4 cortex_m3 -chain-position $_CHIPNAME.m4
-target create $_CHIPNAME.m0 cortex_m3 -chain-position $_CHIPNAME.m0
+# LPC4350 has 96+32 KB SRAM
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x20000
+}
+$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
+			-work-area-size $_WORKAREASIZE -work-area-backup 0
 
-# if srst is not fitted use SYSRESETREQ to
-# perform a soft reset
-cortex_m3 reset_config sysresetreq
+if {![using_hla]} {
+   # on this CPU we should use VECTRESET to perform a soft reset and
+   # manually reset the periphery
+   # SRST or SYSRESETREQ disable the debug interface for the time of
+   # the reset and will not fit our requirements for a consistent debug
+   # session
+   cortex_m reset_config vectreset
+}