X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Flpc4350.cfg;h=fae54f7763ebe38b23f519dc831754e451fa3a21;hb=0baecf99437110356917430af396692fbc53a895;hp=fbbea97d7ff802ab602ec88cacd973b056e99843;hpb=0f1d00bda65975ede19fc20df3b490b08a7c1afd;p=openocd.git diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg index fbbea97d7f..fae54f7763 100644 --- a/tcl/target/lpc4350.cfg +++ b/tcl/target/lpc4350.cfg @@ -1,3 +1,4 @@ +source [find target/swj-dp.tcl] adapter_khz 500 @@ -25,6 +26,12 @@ if { [info exists M4_SWD_TAPID] } { set _M4_SWD_TAPID 0x2ba01477 } +if { [using_jtag] } { + set _M4_TAPID $_M4_JTAG_TAPID +} { + set _M4_TAPID $_M4_SWD_TAPID +} + # # M0 TAP # @@ -34,18 +41,21 @@ if { [info exists M0_JTAG_TAPID] } { set _M0_JTAG_TAPID 0x0ba01477 } -jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \ - -expected-id $_M4_JTAG_TAPID +swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \ + -expected-id $_M4_TAPID +target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4 -jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \ +if { [using_jtag] } { + swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \ -expected-id $_M0_JTAG_TAPID + target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0 +} -target create $_CHIPNAME.m4 cortex_m3 -chain-position $_CHIPNAME.m4 -target create $_CHIPNAME.m0 cortex_m3 -chain-position $_CHIPNAME.m0 - -# on this CPU we should use VECTRESET to perform a soft reset and -# manually reset the periphery -# SRST or SYSRESETREQ disable the debug interface for the time of -# the reset and will not fit our requirements for a consistent debug -# session -cortex_m3 reset_config vectreset +if {![using_hla]} { + # on this CPU we should use VECTRESET to perform a soft reset and + # manually reset the periphery + # SRST or SYSRESETREQ disable the debug interface for the time of + # the reset and will not fit our requirements for a consistent debug + # session + cortex_m reset_config vectreset +}