X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fomap2420.cfg;h=5cf47b21398b082bb988f5e89df843bda1955f95;hb=664ba309d5dac2532c83fed441d14f93c7381d62;hp=9cce2e78974902e6a81a3a08175544fbd9df7f64;hpb=1ac220df71f5e5e016bd3f376c67eb5f3d712612;p=openocd.git

diff --git a/tcl/target/omap2420.cfg b/tcl/target/omap2420.cfg
index 9cce2e7897..5cf47b2139 100644
--- a/tcl/target/omap2420.cfg
+++ b/tcl/target/omap2420.cfg
@@ -6,19 +6,15 @@ if { [info exists CHIPNAME] } {
 } else {
    set  _CHIPNAME omap2420
 }
-if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
-} else {
-   set  _ENDIAN little
-}
 
 # NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK
+reset_config srst_nogate
 
 # Subsidiary TAP:  ARM7TDMIr4 plus imaging ... must add via ICEpick (addr 6).
-jtag newtap $_CHIPNAME iva -irlen 4 -ircapture 0x1 -irmask 0x3f -disable
+jtag newtap $_CHIPNAME iva -irlen 4 -disable
 
 # Subsidiary TAP: C55x DSP ... must add via ICEpick (addr 2).
-jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x1 -irmask 0x3f -disable
+jtag newtap $_CHIPNAME dsp -irlen 38 -disable
 
 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
 if { [info exists ETB_TAPID ] } {
@@ -26,7 +22,7 @@ if { [info exists ETB_TAPID ] } {
 } else {
    set _ETB_TAPID 0x2b900f0f
 }
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID
+jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETB_TAPID
 
 # Subsidiary TAP: ARM1136jf-s with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
 if { [info exists CPU_TAPID ] } {
@@ -34,7 +30,7 @@ if { [info exists CPU_TAPID ] } {
 } else {
    set _CPU_TAPID 0x07b3602f
 }
-jtag newtap $_CHIPNAME arm -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPU_TAPID
+jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID
 
 # Primary TAP: ICEpick-B (JTAG route controller) and boundary scan
 if { [info exists JRC_TAPID ] } {
@@ -42,20 +38,17 @@ if { [info exists JRC_TAPID ] } {
 } else {
    set _JRC_TAPID 0x01ce4801
 }
-jtag newtap $_CHIPNAME jrc -irlen 2 -ircapture 0x1 -irmask 0x3 -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 2 -expected-id $_JRC_TAPID
 
 # GDB target:  the ARM.
 set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm11 -chain-position $_TARGETNAME
 
 # scratch:  framebuffer, may be initially unavailable in some chips
 $_TARGETNAME configure -work-area-phys 0x40210000
 $_TARGETNAME configure -work-area-size 0x00081000
 $_TARGETNAME configure -work-area-backup 0
 
-# trace setup
-# REVISIT ... as of 12-June-2009, OpenOCD's ETM code can't talk to ARM11 cores.
-#etm config $_TARGETNAME 16 normal full etb
-#etb config $_TARGETNAME $_CHIPNAME.etb
-
-# vim:syntax tcl
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb