X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fomap3530.cfg;h=ba130a9cb7eb59a0d831ed1b7895e01a1f4972cd;hb=29d2d15f3fe66d611bc5e9e7ad36af704491a1c1;hp=0a83423c68243319c085a30e07c3a74b4457d8f1;hpb=ac06d41fc723c264e989673be16f9f21a1896518;p=openocd.git

diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 0a83423c68..ba130a9cb7 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -56,7 +56,7 @@ proc omap3_dbginit {target} {
      # General Cortex A8 debug initialisation
      cortex_a8 dbginit
      # Enable DBGU signal for OMAP353x
-     $target mww 0x5401d030 0x00002000
+     $target mww phys 0x5401d030 0x00002000
 }
 
 # be absolutely certain the JTAG clock will work with the worst-case
@@ -65,10 +65,10 @@ proc omap3_dbginit {target} {
 jtag_rclk 1000
 $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
 
-# REVISIT This assumes that SRST is unavailable, so we must assert reset
+# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
 # ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
 # would issue.  RST_DPLL3 (4) is a cold reset.
 set PRM_RSTCTRL 0x48307250
-$_TARGETNAME configure -event reset-assert-pre "$_TARGETNAME mww $PRM_RSTCTRL 2"
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
 
 $_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"