X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fomap3530.cfg;h=ba130a9cb7eb59a0d831ed1b7895e01a1f4972cd;hb=29d2d15f3fe66d611bc5e9e7ad36af704491a1c1;hp=aba6e2558ae95f263483c6cc39f6ba353039c708;hpb=d727e31af99cebff95c41fd1d2b319fddea9edd1;p=openocd.git

diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index aba6e2558a..ba130a9cb7 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -2,9 +2,9 @@
 #  http://focus.ti.com/docs/prod/folders/print/omap3530.html
 # Other OMAP3 chips remove DSP and/or the OpenGL support
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME omap3530
 }
 
@@ -35,34 +35,40 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
 	-expected-id $_JRC_TAPID
 
 # GDB target:  Cortex-A8, using DAP
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
 
-# FIXME when we have A8 support, use it.  A8 != M3 ...
-target create omap3.cpu cortex_m3 -chain-position $_CHIPNAME.dap
-
-# FIXME much of this should be in reset event handlers
-proc omap3_dbginit { } {
-     reset
-     sleep 500
+# SRAM: 64K at 0x4020.0000; use the first 16K
+$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
 
-     jtag tapenable omap3530.dap
-     targets
-     # sleep 1000
-     # dap apsel 1
-     # sleep 1000
-     # dap apsel 1
-     # dap info 1
+###################
 
-     # 0xd401.0000 - ETM
-     # 0xd401.1000 - Cortex-A8
-     # 0xd401.9000 - TPIU (traceport)
-     # 0xd401.b000 - ETB
-     # 0xd401.d000 - DAPCTL
+# the reset sequence is event-driven
+# and kind of finicky...
 
-     omap3.cpu mww 0x54011FB0 0xC5ACCE55
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
 
-     omap3.cpu mdw 0x54011314
-     omap3.cpu mdw 0x54011314
-     # omap3.cpu mdw 0x54011080
+# have the DAP "always" be active
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
 
-     omap3.cpu mww 0x5401d030 0x00002000
+proc omap3_dbginit {target} {
+     # General Cortex A8 debug initialisation
+     cortex_a8 dbginit
+     # Enable DBGU signal for OMAP353x
+     $target mww phys 0x5401d030 0x00002000
 }
+
+# be absolutely certain the JTAG clock will work with the worst-case
+# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
+# OK to speed up *after* PLL and clock tree setup.
+jtag_rclk 1000
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
+
+# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
+# ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
+# would issue.  RST_DPLL3 (4) is a cold reset.
+set PRM_RSTCTRL 0x48307250
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
+
+$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"