X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fomap4430.cfg;h=6e3e78d37fefaa0d95d37c2edb33b385320cc11c;hb=3b39618eb5ab2bcceb00acaba3df303c4d9fa51e;hp=fc3db5d0ccc69214fc95939b5f0c01d0d04df95d;hpb=3fea99097efc1d1a38e73ba646261c2a7a79bd12;p=openocd.git

diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg
index fc3db5d0cc..6e3e78d37f 100644
--- a/tcl/target/omap4430.cfg
+++ b/tcl/target/omap4430.cfg
@@ -16,42 +16,42 @@ source [find target/icepick.cfg]
 #
 # A9 DAP
 #
-if { [info exists DAP_TAPID ] } {
+if { [info exists DAP_TAPID] } {
 	set _DAP_TAPID $DAP_TAPID
 } else {
 	set _DAP_TAPID 0x3BA00477
 }
 
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
 	-expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
+jtag configure $_CHIPNAME.cpu -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 9"
 
 
 #
 # M3 DAPs, one per core
 #
-if { [info exists M3_DAP_TAPID ] } {
+if { [info exists M3_DAP_TAPID] } {
 	set _M3_DAP_TAPID $M3_DAP_TAPID
 } else {
 	set _M3_DAP_TAPID 0x4BA00477
 }
 
-jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \
 	-expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m31_dap -event tap-enable \
+jtag configure $_CHIPNAME.m31 -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 5"
 
-jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \
 	-expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m30_dap -event tap-enable \
+jtag configure $_CHIPNAME.m30 -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 4"
 
 
 #
 # ICEpick-D JRC (JTAG route controller)
 #
-if { [info exists JRC_TAPID ] } {
+if { [info exists JRC_TAPID] } {
 	set _JRC_TAPID $JRC_TAPID
 } else {
 	set _JRC_TAPID  0x3b95c02f
@@ -59,7 +59,7 @@ if { [info exists JRC_TAPID ] } {
 }
 
 # PandaBoard REV EA1 (PEAP platforms)
-if { [info exists JRC_TAPID2 ] } {
+if { [info exists JRC_TAPID2] } {
 	set _JRC_TAPID2 $JRC_TAPID2
 } else {
 	set _JRC_TAPID2 0x1b85202f
@@ -68,7 +68,7 @@ if { [info exists JRC_TAPID2 ] } {
 
 
 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-	-expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2  
+	-expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2
 
 # Required by ICEpick to power-up the debug domain
 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
@@ -93,8 +93,9 @@ set _TARGETNAME $_CHIPNAME.cpu
 set _coreid 0
 set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
 echo "Using dbgbase = [format 0x%x $_dbgbase]"
- 
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
   -coreid 0 -dbgbase $_dbgbase
 
 # SRAM: 56KiB at 0x4030.0000
@@ -104,15 +105,17 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
 #
 # M3 targets, separate TAP/DAP for each core
 #
-target create $_CHIPNAME.m30 cortex_m3 -chain-position $_CHIPNAME.m30_dap
-target create $_CHIPNAME.m31 cortex_m3 -chain-position $_CHIPNAME.m31_dap
+dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30
+dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31
+target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap
+target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap
 
 
 # Once the JRC is up, enable our TAPs
 jtag configure $_CHIPNAME.jrc -event setup "
-	jtag tapenable $_CHIPNAME.dap
-	jtag tapenable $_CHIPNAME.m30_dap
-	jtag tapenable $_CHIPNAME.m31_dap
+	jtag tapenable $_CHIPNAME.cpu
+	jtag tapenable $_CHIPNAME.m30
+	jtag tapenable $_CHIPNAME.m31
 "
 
 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
@@ -124,4 +127,3 @@ $_CHIPNAME.m31 configure -event reset-assert { }
 
 # Soft breakpoints don't currently work due to broken cache handling
 gdb_breakpoint_override hard
-