X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fstellaris.cfg;h=06f27c56807be3df913ec4638558ecd16d5dd46c;hb=85c03753371ed20edc5c03f36a2d2e11730d2239;hp=7fef4ec21ce7dd532ae1078f9a5a1fb53fa45c1e;hpb=af37d5f1960c215d7bbe8d8f2becd4329d6c8e3e;p=openocd.git

diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg
index 7fef4ec21c..06f27c5680 100644
--- a/tcl/target/stellaris.cfg
+++ b/tcl/target/stellaris.cfg
@@ -6,7 +6,7 @@
 
 global _DEVICECLASS
 
-if { [info exists DEVICECLASS ] } {
+if { [info exists DEVICECLASS] } {
    set _DEVICECLASS $DEVICECLASS
 } else {
    set _DEVICECLASS 0xff
@@ -20,18 +20,19 @@ source [find target/swj-dp.tcl]
 # are usable only for ISP style initial flash programming.
 
 if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
+   set _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME lm3s
+   set _CHIPNAME lm3s
 }
 
 # CPU TAP ID 0x1ba00477 for early Sandstorm parts
 # CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
 # CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
-# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest)
+# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm)
+# CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard)
 # ... we'll ignore the JTAG version field, rather than list every
 # chip revision that turns up.
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
    set _CPUTAPID 0x0ba00477
@@ -43,11 +44,11 @@ if { [info exists CPUTAPID ] } {
 swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
  	-expected-id $_CPUTAPID -ignore-version
 
-if { [info exists WORKAREASIZE ] } {
+if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
 } else {
-   # default to 8K working area
-   set _WORKAREASIZE 0x2000
+   # default to 2K working area
+   set _WORKAREASIZE 0x800
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
@@ -55,7 +56,7 @@ target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
 
 # 8K working area at base of ram, not backed up
 #
-# NOTE:  you may need or want to reconfigure the work area;
+# NOTE: you may need or want to reconfigure the work area;
 # some parts have just 6K, and you may want to use other
 # addresses (at end of mem not beginning) or back it up.
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
@@ -63,7 +64,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 # JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
 # LM3S parts don't support RTCK
 #
-# NOTE:  this may be increased by a reset-init handler, after it
+# NOTE: this may be increased by a reset-init handler, after it
 # configures and enables the PLL.  Or you might need to decrease
 # this, if you're using a slower clock.
 adapter_khz 500
@@ -132,7 +133,7 @@ proc reset_peripherals {family} {
 $_TARGETNAME configure -event reset-start {
 	adapter_khz 500
 
-	#	
+	#
 	# When nRST is asserted on most Stellaris devices, it clears some of
 	# the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
 	# and OpenOCD depends on those TRMs.  So we won't use SRST on those
@@ -153,11 +154,12 @@ $_TARGETNAME configure -event reset-start {
 	   set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
 	}
 
-	if {$device_class == 0 || $device_class == 1 || $device_class == 3} {
-		# Sandstorm, Fury and DustDevil are able to use NVIC SYSRESETREQ
+	if {$device_class == 0 || $device_class == 1 ||
+		$device_class == 3 || $device_class == 5} {
+		# Sandstorm, Fury, DustDevil and Blizzard are able to use NVIC SYSRESETREQ
 		cortex_m3 reset_config sysresetreq
 	} else {
-		# Tempest and newer default to using NVIC VECTRESET
+		# Tempest and Firestorm default to using NVIC VECTRESET
 		# peripherals will need reseting manually, see proc reset_peripherals
 		cortex_m3 reset_config vectreset