X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32f3x.cfg;h=318d96c656c12b370a3b95d13e4adde37a9efa2d;hb=18d6c0b02bf5e1318d5f5484b5ba68b476a418f0;hp=3d68c4bfbafe657d5453fbb8edb0bf2c58001a83;hpb=acc4bb83fd1f26a677fdc2c8ccdc7a235f877d2d;p=openocd.git

diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index 3d68c4bfba..318d96c656 100644
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -11,11 +11,7 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME stm32f3x
 }
 
-if { [info exists ENDIAN] } {
-   set _ENDIAN $ENDIAN
-} else {
-   set _ENDIAN little
-}
+set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
 # By default use 16kB
@@ -34,7 +30,7 @@ if { [info exists WORKAREASIZE] } {
 adapter_khz 1000
 
 adapter_nsrst_delay 100
-if {$using_jtag} {
+if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
 
@@ -42,9 +38,13 @@ if {$using_jtag} {
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
-  # See STM Document RM0316
-  # Section 29.6.3 - corresponds to Cortex-M4 r0p1
-   set _CPUTAPID 0x4ba00477
+   if { [using_jtag] } {
+      # See STM Document RM0316
+      # Section 29.6.3 - corresponds to Cortex-M4 r0p1
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
@@ -52,14 +52,26 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU
 if { [info exists BSTAPID] } {
    set _BSTAPID $BSTAPID
 } else {
-  # STM Document RM0316 rev 2 Section 30.6.2 says 0x06432041
-  # but STM32F303VCT6 rev Y has 0x06422041
+  # STM Document RM0316 rev 5 for STM32F302/303 B/C size
   set _BSTAPID1 0x06422041
+  # STM Document RM0313 rev 3 for STM32F37x
   set _BSTAPID2 0x06432041
+  # STM Document RM0313 rev 3 for STM32F37x Chip Revision 1.0
+  set _BSTAPID3 0x06422041
+  #  STM Document RM364 rev 1 for STM32F334
+  set _BSTAPID4 0x06438041
+  #  STM Document RM316 rev 5 for STM32F303 6/8 size
+  #  STM Document RM365 rev 3 for STM32F302 6/8 size
+  #  STM Document RM366 rev 2 for STM32F301 6/8 size
+  set _BSTAPID5 0x06439041
+  #  STM Document RM016 rev 5 for STM32F303 D/E size
+  set _BSTAPID6 0x06446041
 }
 
-if {$using_jtag} {
- jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
+if {[using_jtag]} {
+ swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+ -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4 \
+ -expected-id $_BSTAPID5 -expected-id $_BSTAPID6
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
@@ -70,6 +82,10 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
 
-# if srst is not fitted use SYSRESETREQ to
-# perform a soft reset
-cortex_m reset_config sysresetreq
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}