X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fstm32l0.cfg;h=417b282d3838b1c29a8e2ce5b0a6370812fccac2;hb=72740904568414bb4a9192fe89034bae3b1a9e45;hp=fc2751e9585081dd54e8d5179561962b96861712;hpb=c3ec1940b52e5d3f47c5c96bea2430b4444d83ea;p=openocd.git

diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg
index fc2751e958..417b282d38 100644
--- a/tcl/target/stm32l0.cfg
+++ b/tcl/target/stm32l0.cfg
@@ -4,6 +4,7 @@
 #
 
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -11,12 +12,14 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME stm32l0
 }
 
+set _ENDIAN little
+
 # Work-area is a space in RAM used for flash programming
-# By default use 8kB (max ram on smallest part)
+# By default use 2kB (max ram on smallest part)
 if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
 } else {
-   set _WORKAREASIZE 0x2000
+   set _WORKAREASIZE 0x800
 }
 
 # JTAG speed should be <= F_CPU/6.
@@ -36,7 +39,7 @@ if { [info exists CPUTAPID] } {
 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -44,6 +47,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
 
+reset_config srst_nogate
+
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
@@ -71,3 +76,12 @@ $_TARGETNAME configure -event reset-init {
 $_TARGETNAME configure -event reset-start {
 	adapter_khz 300
 }
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0x40015804 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0x40015808 0x00001800 0
+}