X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fstr912.cfg;h=38545ac905c27e68adb4780c53e8ddfa83c15627;hb=f8a6a07149d88737f3d466e7ce620cc1f0874c6a;hp=599a254a043354ae55b2157066214c06301c1552;hpb=bbc193ef8d25243a8f7e861de3a8820206939e9c;p=openocd.git

diff --git a/tcl/target/str912.cfg b/tcl/target/str912.cfg
index 599a254a04..38545ac905 100644
--- a/tcl/target/str912.cfg
+++ b/tcl/target/str912.cfg
@@ -13,7 +13,7 @@ if { [info exists ENDIAN] } {
 }
 
 # jtag speed. We need to stick to 16kHz until we've finished reset.
-jtag_rclk 16
+adapter_khz 16
 
 adapter_nsrst_delay 100
 jtag_ntrst_delay 100
@@ -48,11 +48,11 @@ jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BST
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
 
-$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
+$_TARGETNAME configure -event reset-start { adapter_khz 16 }
 
 $_TARGETNAME configure -event reset-init {
 	# We can increase speed now that we know the target is halted.
-	#jtag_rclk 3000
+	#adapter_khz 3000
 
 	# -- Enable 96K RAM
 	# PFQBC enabled / DTCM & AHB wait-states disabled