X-Git-Url: https://review.openocd.org/gitweb?a=blobdiff_plain;f=tcl%2Ftarget%2Fti_tms570.cfg;h=ce3a17696eaa9e263839220a2bc61b07cde84131;hb=96903e6df43e2bc967267e034edf15a7c274d044;hp=b8f9287f41b620b7e901c9719ddeeec4448ae921;hpb=a1719e004865fb9ca556f693fd8e5c56992bc1de;p=openocd.git

diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti_tms570.cfg
index b8f9287f41..ce3a17696e 100644
--- a/tcl/target/ti_tms570.cfg
+++ b/tcl/target/ti_tms570.cfg
@@ -20,31 +20,48 @@ source [find target/icepick.cfg]
 if { [info exists DAP_TAPID] } {
 	set _DAP_TAPID $DAP_TAPID
 }
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
 
 # ICEpick-C (JTAG route controller)
 # JRC_TAPID should be set before source-ing this file
 if { [info exists JRC_TAPID] } {
 	set _JRC_TAPID $JRC_TAPID
 }
+
+set _JRC_TAPID2 0x0B7B302F
+set _JRC_TAPID3 0x0B95502F
+set _JRC_TAPID4 0x0B97102F
+set _JRC_TAPID5 0x0D8A002F
+set _JRC_TAPID6 0x2B8A002F
+set _JRC_TAPID7 0x2D8A002F
+set _JRC_TAPID8 0x3B8A002F
+set _JRC_TAPID9 0x3D8A002F
+
+
 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-	-expected-id $_JRC_TAPID -ignore-version
-jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
+	-expected-id $_JRC_TAPID \
+	-expected-id $_JRC_TAPID2 \
+	-expected-id $_JRC_TAPID3 \
+	-expected-id $_JRC_TAPID4 \
+	-expected-id $_JRC_TAPID5 \
+	-expected-id $_JRC_TAPID6 \
+	-expected-id $_JRC_TAPID7 \
+	-expected-id $_JRC_TAPID8 \
+	-expected-id $_JRC_TAPID9 \
+	-ignore-version
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
 
-# Cortex R4 target
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Cortex-R4 target
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \
-	-chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003
+	-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003
 
 # TMS570 uses quirky BE-32 mode
-$_TARGETNAME dap ti_be_32_quirks 1
-
-$_TARGETNAME configure -event gdb-attach {
-	cortex_r4 dbginit
-	halt
-}
+$_CHIPNAME.dap ti_be_32_quirks 1
 
 $_TARGETNAME configure -event "reset-assert" {
 	global _CHIPNAME