target/mips32: pracc write cp0 status register first

When user requested a change on cp0 status register,
it may contain changes on EXL/ERL bits, and changes on
these bits could lead to differnt behaviours on writing
to other cp0 registers.

Change-Id: Ic83039988c29c06ee134226b52de943c46d19da2
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7914
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index 9f0d87cd9833b6454fa25655067a8fdde1115424..db50ef9285ce79f34e3dbbae3e6047cdd554038f 100644 (file)
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -842,12 +842,12 @@ int mips32_pracc_write_regs(struct mips32_common *mips32)
        };
 
        uint32_t cp0_write_data[] = {
+               /* status */
+               c0rs[0],
                /* lo */
                gprs[32],
                /* hi */
                gprs[33],
-               /* status */
-               c0rs[0],
                /* badvaddr */
                c0rs[1],
                /* cause */
@@ -856,6 +856,9 @@ int mips32_pracc_write_regs(struct mips32_common *mips32)
                c0rs[3],
        };
 
+       /* Write CP0 Status Register first, changes on EXL or ERL bits
+        * may lead to different behaviour on writing to other CP0 registers.
+        */
        for (size_t i = 0; i < ARRAY_SIZE(cp0_write_code); i++) {
                /* load CP0 value in $1 */
                pracc_add_li32(&ctx, 1, cp0_write_data[i], 0);