aarch64: Add support for ARMv8-R

ARMv8-R platforms are similar to ARMv8-A regarding
JTAG and most cpu registers. ARMv8-R doesn't has MMU
but has MPU instead.

ARMv8-R platforms can be AArch32 only such as Cortex-R52,
or AArch64 capable like Cortex-R82.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Change-Id: Ib086f71685d1e3704b396d478ae9399dd8a391e1
Reviewed-on: https://review.openocd.org/c/openocd/+/6843
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 3c33032e976c84a97333fcfa5a968a89578dd781..6c9673fa23b98981e9631c43dd7b20ce5f3acbff 100644 (file)
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -1066,9 +1066,12 @@ static int aarch64_post_debug_entry(struct target *target)
                armv8_identify_cache(armv8);
                armv8_read_mpidr(armv8);
        }
-
-       armv8->armv8_mmu.mmu_enabled =
+       if (armv8->is_armv8r) {
+               armv8->armv8_mmu.mmu_enabled = 0;
+       } else {
+               armv8->armv8_mmu.mmu_enabled =
                        (aarch64->system_control_reg & 0x1U) ? 1 : 0;
+       }
        armv8->armv8_mmu.armv8_cache.d_u_cache_enabled =
                (aarch64->system_control_reg & 0x4U) ? 1 : 0;
        armv8->armv8_mmu.armv8_cache.i_cache_enabled =
@@ -2726,6 +2729,25 @@ static int aarch64_init_arch_info(struct target *target,
        return ERROR_OK;
 }
 
+static int armv8r_target_create(struct target *target, Jim_Interp *interp)
+{
+       struct aarch64_private_config *pc = target->private_config;
+       struct aarch64_common *aarch64;
+
+       if (adiv5_verify_config(&pc->adiv5_config) != ERROR_OK)
+               return ERROR_FAIL;
+
+       aarch64 = calloc(1, sizeof(struct aarch64_common));
+       if (!aarch64) {
+               LOG_ERROR("Out of memory");
+               return ERROR_FAIL;
+       }
+
+       aarch64->armv8_common.is_armv8r = true;
+
+       return aarch64_init_arch_info(target, aarch64, pc->adiv5_config.dap);
+}
+
 static int aarch64_target_create(struct target *target, Jim_Interp *interp)
 {
        struct aarch64_private_config *pc = target->private_config;
@@ -2740,6 +2762,8 @@ static int aarch64_target_create(struct target *target, Jim_Interp *interp)
                return ERROR_FAIL;
        }
 
+       aarch64->armv8_common.is_armv8r = false;
+
        return aarch64_init_arch_info(target, aarch64, pc->adiv5_config.dap);
 }
 
@@ -2762,12 +2786,16 @@ static void aarch64_deinit_target(struct target *target)
 
 static int aarch64_mmu(struct target *target, int *enabled)
 {
+       struct aarch64_common *aarch64 = target_to_aarch64(target);
+       struct armv8_common *armv8 = &aarch64->armv8_common;
        if (target->state != TARGET_HALTED) {
                LOG_ERROR("%s: target %s not halted", __func__, target_name(target));
                return ERROR_TARGET_INVALID;
        }
-
-       *enabled = target_to_aarch64(target)->armv8_common.armv8_mmu.mmu_enabled;
+       if (armv8->is_armv8r)
+               *enabled = 0;
+       else
+               *enabled = target_to_aarch64(target)->armv8_common.armv8_mmu.mmu_enabled;
        return ERROR_OK;
 }
 
@@ -3165,3 +3193,39 @@ struct target_type aarch64_target = {
        .mmu = aarch64_mmu,
        .virt2phys = aarch64_virt2phys,
 };
+
+struct target_type armv8r_target = {
+       .name = "armv8r",
+
+       .poll = aarch64_poll,
+       .arch_state = armv8_arch_state,
+
+       .halt = aarch64_halt,
+       .resume = aarch64_resume,
+       .step = aarch64_step,
+
+       .assert_reset = aarch64_assert_reset,
+       .deassert_reset = aarch64_deassert_reset,
+
+       /* REVISIT allow exporting VFP3 registers ... */
+       .get_gdb_arch = armv8_get_gdb_arch,
+       .get_gdb_reg_list = armv8_get_gdb_reg_list,
+
+       .read_memory = aarch64_read_phys_memory,
+       .write_memory = aarch64_write_phys_memory,
+
+       .add_breakpoint = aarch64_add_breakpoint,
+       .add_context_breakpoint = aarch64_add_context_breakpoint,
+       .add_hybrid_breakpoint = aarch64_add_hybrid_breakpoint,
+       .remove_breakpoint = aarch64_remove_breakpoint,
+       .add_watchpoint = aarch64_add_watchpoint,
+       .remove_watchpoint = aarch64_remove_watchpoint,
+       .hit_watchpoint = aarch64_hit_watchpoint,
+
+       .commands = aarch64_command_handlers,
+       .target_create = armv8r_target_create,
+       .target_jim_configure = aarch64_jim_configure,
+       .init_target = aarch64_init_target,
+       .deinit_target = aarch64_deinit_target,
+       .examine = aarch64_examine,
+};

diff --git a/src/target/armv8.h b/src/target/armv8.h
index 54aa08634ccdb3c0256a392013c55212696444c1..f5aa211097d5dc5e96f5ff42bd03aa2246c79c52 100644 (file)
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -204,6 +204,7 @@ struct armv8_common {
        uint8_t pa_size;
        uint32_t page_size;
        uint64_t ttbr_base;
+       bool is_armv8r;
 
        struct armv8_mmu_common armv8_mmu;
 

diff --git a/src/target/target.c b/src/target/target.c
index 47abd2823193f016f03a6810e92d82be4966758a..6c0f4afb13bd70e04ebef8278d76e65bf10f73d4 100644 (file)
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -82,6 +82,7 @@ extern struct target_type cortexm_target;
 extern struct target_type cortexa_target;
 extern struct target_type aarch64_target;
 extern struct target_type cortexr4_target;
+extern struct target_type armv8r_target;
 extern struct target_type arm11_target;
 extern struct target_type ls1_sap_target;
 extern struct target_type mips_m4k_target;
@@ -141,6 +142,7 @@ static struct target_type *target_types[] = {
        &esirisc_target,
        &arcv2_target,
        &aarch64_target,
+       &armv8r_target,
        &mips_mips64_target,
        NULL,
 };