zy1000: FPGA revC wip

The bug in revC register memory access is pretty much
cornered now.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>

diff --git a/src/jtag/zy1000/jtag_minidriver.h b/src/jtag/zy1000/jtag_minidriver.h
index afbea13a4509ebd3dddbbceffe0a9ad22a78825d..536c677061d3d97c92af3d60a25aa056807a3745 100644 (file)
--- a/src/jtag/zy1000/jtag_minidriver.h
+++ b/src/jtag/zy1000/jtag_minidriver.h
@@ -18,6 +18,7 @@
  ***************************************************************************/
 
 #include <cyg/hal/hal_io.h>             // low level i/o
+#include <cyg/hal/hal_intr.h>             // low level i/o
 
 //#define VERBOSE(a) a
 #define VERBOSE(a)
@@ -31,10 +32,16 @@ int  diag_printf(const char *fmt, ...);
 #define ZY1000_PEEK(a, b) HAL_READ_UINT32(a, b); diag_printf("peek 0x%08x = 0x%08x\n", a, b)
 #else
 #define ZY1000_PEEK(a, b) HAL_READ_UINT32(a, b)
-#define ZY1000_POKE(a, b) HAL_WRITE_UINT32(a, b);\
- {/* This will flush the bridge FIFO. Overflowed bridge FIFO fails. We must \
- flush every "often". No precise system has been found, but 4 seems solid. \
-  */ \
+
+#ifdef CYGPKG_HAL_NIOS2
+#define ZY1000_POKE(a, b) \
+                {/* This will flush the bridge FIFO. Overflowed bridge FIFO fails. We must \
+                flush every "often". No precise system has been found, but 4 seems solid. \
+                 This code goes away once the FPGA has been fixed. */ \
+\
+CYG_INTERRUPT_STATE _old_; \
+HAL_DISABLE_INTERRUPTS(_old_); \
+HAL_WRITE_UINT32(a, b);\
  static int overflow_counter = 0; \
    if (++overflow_counter >= 1) \
    { \
@@ -42,7 +49,14 @@ int  diag_printf(const char *fmt, ...);
           cyg_uint32 empty; ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, empty); \
           overflow_counter = 0; \
    } \
- }
+   /* NB! interrupts must be restored *after* read */ \
+   HAL_RESTORE_INTERRUPTS(_old_); \
+}\
+
+#else
+#define ZY1000_POKE(a, b) HAL_WRITE_UINT32(a, b)
+#endif
+
 #endif
 
 // FIFO empty?