int retval;
uint32_t baseptr_upper, baseptr_lower;
- baseptr_upper = 0;
-
- if (is_64bit_ap(ap)) {
- /* Read higher order 32-bits of base address */
- retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseptr_upper);
+ if (ap->cfg_reg == MEM_AP_REG_CFG_INVALID) {
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &ap->cfg_reg);
if (retval != ERROR_OK)
return retval;
}
-
retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, &baseptr_lower);
if (retval != ERROR_OK)
return retval;
retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
if (retval != ERROR_OK)
return retval;
+ /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
+ if (ap->cfg_reg == MEM_AP_REG_CFG_INVALID || is_64bit_ap(ap)) {
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseptr_upper);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
+ if (!is_64bit_ap(ap))
+ baseptr_upper = 0;
*dbgbase = (((target_addr_t)baseptr_upper) << 32) | baseptr_lower;
return ERROR_OK;
ap = dap_ap(dap, apsel);
retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, &baseaddr_lower);
- if (is_64bit_ap(ap) && retval == ERROR_OK)
+ if (retval == ERROR_OK && ap->cfg_reg == MEM_AP_REG_CFG_INVALID)
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &ap->cfg_reg);
+
+ if (retval == ERROR_OK && (ap->cfg_reg == MEM_AP_REG_CFG_INVALID || is_64bit_ap(ap))) {
+ /* MEM_AP_REG_BASE64 is defined as 'RES0'; can be read and then ignored on 32 bits AP */
retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseaddr_upper);
+ }
+
+ if (retval == ERROR_OK)
+ retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
- retval = dap_run(dap);
- if (retval != ERROR_OK)
- return retval;
+
if (is_64bit_ap(ap)) {
baseaddr = (((target_addr_t)baseaddr_upper) << 32) | baseaddr_lower;
command_print(CMD, "0x%016" PRIx64, baseaddr);
} else
command_print(CMD, "0x%08" PRIx32, baseaddr_lower);
- return retval;
+ return ERROR_OK;
}
COMMAND_HANDLER(dap_memaccess_command)
#define CSW_APB_DEFAULT (CSW_DBGSWENABLE)
/* Fields of the MEM-AP's CFG register */
-#define MEM_AP_REG_CFG_BE BIT(0)
-#define MEM_AP_REG_CFG_LA BIT(1)
-#define MEM_AP_REG_CFG_LD BIT(2)
+#define MEM_AP_REG_CFG_BE BIT(0)
+#define MEM_AP_REG_CFG_LA BIT(1)
+#define MEM_AP_REG_CFG_LD BIT(2)
+#define MEM_AP_REG_CFG_INVALID 0xFFFFFFF8
/* Fields of the MEM-AP's IDR register */
#define IDR_REV (0xFUL << 28)
extern const struct dap_ops jtag_dp_ops;
extern struct adapter_driver *adapter_driver;
-#define ADI_BAD_CFG 0xBAD00000
-
/* DAP command support */
struct arm_dap_object {
struct list_head lh;
dap->ap[i].tar_autoincr_block = (1<<10);
/* default CSW value */
dap->ap[i].csw_default = CSW_AHB_DEFAULT;
- dap->ap[i].cfg_reg = ADI_BAD_CFG; /* mem_ap configuration reg (large physical addr, etc.) */
+ dap->ap[i].cfg_reg = MEM_AP_REG_CFG_INVALID; /* mem_ap configuration reg (large physical addr, etc.) */
}
INIT_LIST_HEAD(&dap->cmd_journal);
INIT_LIST_HEAD(&dap->cmd_pool);