cortex_m: add detection of MVE feature for Armv8.1-M cores For Armv8.1-M based cores, detect if the core implements the optional M-profile vector extension (MVE), using MVFR1 register. While at there rework armv7m->fp_feature detection based on MVFR0 and MVFR1 registers. Change-Id: I92d5b1759aea9f7561d285f46acdec51d6efb7b4 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6950 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
target: use unsigned int for timeout_ms Change the prototype of functions: - target_run_algorithm() - target_wait_algorithm() - target_wait_state() - struct target_type::run_algorithm() - struct target_type::wait_algorithm() to use unsigned int for timeout_ms instead of int. Change accordingly the variables passed as parameter. Change-Id: I0b8d6e691bb3c749eeb2911dc5a86c38cc0cb65d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7562 Tested-by: jenkins
openocd: remove CamelCase symbols *xPSR* We have left the camelcase symbols *xPSR* for some time, to avoid any conflict with possibly pending patches in gerrit. With the approaching v0.12.0-rc1, it's time to revisit it. The patches in gerrit that conflict with this rename are all not merge-able due to conflicts or due to negative review. Drop these CamelCase symbols. Change-Id: Ifbac4c1df9cc55994e024971a2aaebeed2ea4ed3 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7155 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
target: consolidate existing target/algo common_magic Unify common_magic type to unsigned int Move common_magic to be the first member of the struct Add unsigned specifier to xxx_COMMON_MAGIC #defines Change-Id: If961d33232698529514ba3720e04418baf6dc6fe Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6996 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
openocd: src/target: replace the GPL-2.0-or-later license tag Replace the FSF boilerplate with the SPDX tag. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: I255ad17235ff1e01bf0aa4deed4d944e1d693ddb Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7071 Tested-by: jenkins
target/armv7m,cortex_m: introduce checked arch_info cast routines target_to_armv7m() and target_to_cm() do not match the magic number so they are not suitable for use outside of target driver code. Add checked versions of pointer getters. Match the magic number to ensure the returned value points to struct of the correct type. Change-Id: If90ef7e969ef04f0f2103e0da29dcbe8e1ac1c0d Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6750 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
target/cortex_m: faster reading of all CPU registers Without the change cortex_m_debug_entry() reads all registers calling cortex_m_load_core_reg_u32() for each register with a poor usage of JTAG/SWD queue. It is time consuming, especially on an USB FS based adapter. Moreover if target_request debugmsgs are enabled, DCB_DCRDR is saved and restored on each register read. This change introduces cortex_m_fast_read_all_regs() which queues all register reads and a single dap_run() transaction does all work. cortex_m_fast_read_all_regs() reads all registers unconditionally regardless register cache is valid or not. This is a difference from the original cortex_m_debug_entry() code. cortex_m_debug_entry times from -d3 log, Cortex-M4F and CMSIS-DAP (Kinetis K28F-FRDM kit) target_request | time [ms] debugmsgs | without the change | with the change ---------------+--------------------+----------------- disable | 186 | 27 enable | 232 | 29 Added checking of DHCSR.S_REGRDY flag. If "not ready" is seen, cortex_m->slow_register_read is set and fallback to the old register read method cortex_m_slow_read_all_regs() is used instead of cortex_m_fast_read_all_regs(). Change-Id: I0665d94b97ede217394640871dc451ec93410254 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/5321 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
armv7m.h: relax dependency from 'arm_adi_v5.h' The include file 'armv7m.h' includes 'arm_adi_v5.h' only to get the definition of 'struct adiv5_ap', but doesn't need the struct content. Reducing the cross dependencies speeds-up the compile time during code development by avoiding re-compiling file. Relax the dependency by locally declaring 'struct adiv5_ap' in 'armv7m.h' and remove the include of 'arm_adi_v5.h'. Fix the other files that have now lost the includes file that 'arm_adi_v5.h' depends from. Change-Id: Ic0d40b17db6045fa43f348bda83eaf211a6b347d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6468 Tested-by: jenkins Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
armv7m: replace flag 'stlink' with 'is_hla_target' The HLA target is not anymore used by ST-Link only, but required by Nu-Link and TI-ICDI too. Rename the flag 'stlink' as 'is_hla_target'. Change-Id: Id2ee2c0a1e8bf1f1e899f7a560140c34eefeeee5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6206 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
target/armv7m.h: [style] replace tab with space between variable type and name Change-Id: I9740c25857295a2a655d3046322a3f23f0ee7f78 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/6230 Reviewed-by: Marc Schink <dev@zapb.de> Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
cortex_m: add armv8m special registers Change-Id: I1942f375a5f4282ad1fe4a2ff3b8f3cbc64d8f7f Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/6016 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
cortex_m: mark FPU register as non-existent instead of playing with num_regs Change-Id: Iac7c5bfbb95c8d9a8c6d65104d138692a44eca78 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/6015 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
target/armv7m: change FPv4_SP and FPv5_SP/DP identifiers to uppercase Change-Id: Ia421a973e5fb4767715c9f95c91745f8ca1de1da Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/6177 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
target/armv7m: rework Cortex-M register handling part 3 Move primask/basepri/faultmask/control packing/unpacking from cortex_m.c and hla_target.c to armv7m.c armv7m_read_core_reg() and armv7m_write_core_reg() where also the FP 32/64-bit registers conversion takes place. Introduce a new hidden register ARMV7M_PMSK_BPRI_FLTMSK_CTRL for packing/unpacking of special registers in the register cache. The new packing/unpacking is endianess safe. While on it improve returned error codes and LOG_ messages. Just minimal changes in cortex_m.c and hla_target.c, will be consolidated in the next patch. Change-Id: Id51e764e243e54b5fdaadf2a202eee7c4bc729fe Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5863 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
target/armv7m: rework Cortex-M register handling part 2 Make arm register id coherent with reg_list index. Without this reg_list[ARMV7M_R12] was possible but reg_list[ARMV7M_FPSCR] was out of bounds. Remove unused items from reg_list index. Change-Id: I84d3b5c496fc1839d07a5b74cb1fd1c3d4ff8989 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5862 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com>
target/armv7m: rework Cortex-M register handling part 1 Define a new enum with DCRSR.REGSEL selectors. Introduce armv7m_map_id_to_regsel() to unify mapping in one place. Use DCRSR.REGSEL selectors for low level register read/write. Change-Id: Ida0ccdfa9cdb1257a1900b8bfbf172b076374d39 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5327 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com>
target, flash: prepare infrastructure for multi-block blank check 'flash erase_check' command runs a check algorithm on a target if possible. The algorithm is run repeatedly for each flash sector. Unfortunately every start and stop of the algorithm impose not negligible overhead. In practice it means checking is faster than plain read only for sectors of size approx 4 kByte or bigger. And checking sectors as short as 512 bytes runs approx 4 times slower than plain read. The patch changes API call target_blank_check_memory() and related to take an array of sectors (or arbitrary memory blocks). Changes in target-specific checking routines are kept minimal. They use only the first block from the array and process it by the unchanged algorithm. default_flash_blank_check() routine repeats target_blank_check_memory() until all blocks are checked, so it works with both multi-block and single-block based checkers. Change-Id: I0e6c60f2d71364c9c07c09416b04de9268807f5e Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4297 Tested-by: jenkins Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
target: Constify parameter of is_armv7m() Change-Id: Ieea1b0dec88818e9e8d5c8c5d54aa8959556d77b Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4275 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
target: Add 64-bit target address support Define a target_addr_t type to support 32-bit and 64-bit addresses at the same time. Also define matching TARGET_PRI*ADDR format macros as well as a convenient TARGET_ADDR_FMT. In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000) be least invasive by leaving the formatting unchanged apart from the type; for generic code adopt TARGET_ADDR_FMT as unified address format. Don't silently change gdb formatting here, leave that to later. Add COMMAND_PARSE_ADDRESS() macro to abstract the address type. Implement it using its own parse_target_addr() function, in the hopes of catching pointer type mismatches better. Add '--disable-target64' configure option to revert to previous 32-bit target address behavior. Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> [AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
flash/nor: Add erased_value to drivers and pass it to targets struct flash_driver has a default_padded_value field that is similar, but it can be changed by the user for the specific purpose of padding. Add a new erased_value field and initialize it for all targets, particularly stm32lx, xmc4xxx and virtual. Use this value in core.c:default_flash_mem_blank_check(), the slow path. Extend the target API to pass erased_value down to target code. Adding an argument ensures that we catch all callers. This allows us to merge xmc4xxx.c:xmc4xxx_blank_check_memory() into armv7m:armv7m_blank_check_memory(). It further allows us to use default_flash_blank_check() in place of xmc4xxx.c:xmc4xxx_flash_blank_check(), adding a potential slow path fallback, as well as stm32lx:stm32lx_erase_check(), adding the potential armv7m fast path with fallback to default_flash_mem_blank_check(). Fix a mips32 code comment while at it (zeroed -> erased). The armv4_5 and mips32 target implementations will now error out if an erase value other than 0xff is used, causing default_flash_blank_check() to fall back to the default_flank_mem_blank_check() slow path. Change-Id: I39323fbbc4b71c256cd567e439896d0245d4745f Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3497 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>