contrib/loaders/flash/efm32.S

   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Andreas Fritiofson                              *
   3  *   andreas.fritiofson@gmail.com                                          *
   4  *   Copyright (C) 2013 by Roman Dmitrienko                                *
   5  *   me@iamroman.org                                                       *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  21  ***************************************************************************/
  22
  23         .text
  24         .syntax unified
  25         .cpu cortex-m0
  26         .thumb
  27         .thumb_func
  28
  29         /* Params:
  30          * r0 - flash base (in), status (out)
  31          * r1 - count (word-32bit)
  32          * r2 - workarea start
  33          * r3 - workarea end
  34          * r4 - target address
  35          * Clobbered:
  36          * r5 - rp
  37          * r6 - wp, tmp
  38          * r7 - tmp
  39          */
  40
  41 /* offsets of registers from flash reg base */
  42 #define EFM32_MSC_WRITECTRL_OFFSET      0x008
  43 #define EFM32_MSC_WRITECMD_OFFSET       0x00c
  44 #define EFM32_MSC_ADDRB_OFFSET          0x010
  45 #define EFM32_MSC_WDATA_OFFSET          0x018
  46 #define EFM32_MSC_STATUS_OFFSET         0x01c
  47 #define EFM32_MSC_LOCK_OFFSET           0x03c
  48
  49         /* unlock MSC */
  50         ldr     r6, =#0x1b71
  51         str     r6, [r0, #EFM32_MSC_LOCK_OFFSET]
  52         /* set WREN to 1 */
  53         movs    r6, #1
  54         str     r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET]
  55
  56 wait_fifo:
  57         ldr     r6, [r2, #0]    /* read wp */
  58         cmp     r6, #0          /* abort if wp == 0 */
  59         beq     exit
  60         ldr     r5, [r2, #4]    /* read rp */
  61         cmp     r5, r6          /* wait until rp != wp */
  62         beq     wait_fifo
  63
  64         /* store address in MSC_ADDRB */
  65         str     r4, [r0, #EFM32_MSC_ADDRB_OFFSET]
  66         /* set LADDRIM bit */
  67         movs    r6, #1
  68         str     r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
  69         /* check status for INVADDR and/or LOCKED */
  70         ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET]
  71         movs    r7, #6
  72         tst     r6, r7
  73         bne     error
  74
  75         /* wait for WDATAREADY */
  76 wait_wdataready:
  77         ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET]
  78         movs    r7, #8
  79         tst     r6, r7
  80         beq     wait_wdataready
  81
  82         /* load data to WDATA */
  83         ldr     r6, [r5]
  84         str     r6, [r0, #EFM32_MSC_WDATA_OFFSET]
  85         /* set WRITEONCE bit */
  86         movs    r6, #8
  87         str     r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
  88
  89         adds    r5, #4          /* rp++ */
  90         adds    r4, #4          /* target_address++ */
  91
  92         /* wait until BUSY flag is reset */
  93 busy:
  94         ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET]
  95         movs    r7, #1
  96         tst     r6, r7
  97         bne     busy
  98
  99         cmp     r5, r3          /* wrap rp at end of buffer */
 100         bcc     no_wrap
 101         mov     r5, r2
 102         adds    r5, #8
 103 no_wrap:
 104         str     r5, [r2, #4]    /* store rp */
 105         subs    r1, r1, #1      /* decrement word count */
 106         cmp     r1, #0
 107         beq     exit            /* loop if not done */
 108         b       wait_fifo
 109 error:
 110         movs    r0, #0
 111         str     r0, [r2, #4]    /* set rp = 0 on error */
 112 exit:
 113         mov     r0, r6          /* return status in r0 */
 114         bkpt    #0